Segmented Charge-Trap Stack for 3D NAND Data Retention

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Solution Overview

Problem

Conventional NAND memory architectures face data retention issues due to charge migration between memory cells caused by charge-trapping material extending across multiple cells, leading to inefficiencies in charge storage and retrieval.

Innovation Solution

The implementation of vertically-spaced segments of charge-trapping material with low-k dielectric material in between, along with a specific stack configuration and processing steps, to impede charge migration and enhance data retention by using alternating insulative and conductive layers in a three-dimensional NAND memory array.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If charge-trapping material extends across multiple memory cells, then charge storage capacity is increased, but charge migration between cells occurs causing data retention issues

Engineering Contradiction:
Improvecharge storage capacityVSAvoiddata retention
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The charge-trapping material is divided into vertically-spaced segments separated by insulative material layers. This segmentation prevents charge migration between memory cells while maintaining adequate charge storage capacity within each segment, resolving the contradiction between storage capacity and data retention reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Insulative material layers are introduced as intermediaries between segments of charge-trapping material. These intermediary layers block charge migration pathways between cells while allowing each segment to maintain its charge storage function, thus improving data retention without significantly reducing overall storage capacity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If vertically-spaced segments of charge-trapping material are used, then charge migration is reduced, but device complexity increases

Engineering Contradiction:
Improvecharge storage isolationVSAvoidstack configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The insulative material layers serve multiple functions simultaneously: they electrically isolate charge-trapping segments, provide structural support for the vertical stack, and act as separation layers during fabrication processes. This merging of functions reduces the need for additional dedicated components, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The alternating stack of insulative material and charge-trapping material creates a multi-functional structure where each layer contributes to electrical isolation, charge storage, and structural integrity. This universal design approach allows a single configuration to address multiple requirements, reducing overall device complexity despite the segmented architecture.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces charge migration between memory cells, improving data retention and operational efficiency by using low-k dielectric material to alleviate capacitive coupling and employing a structured stack to manage charge storage and retrieval.

Implementation Method 1

low-k dielectric material to alleviate capacitive coupling

Methodology Applied
Scientific EffectCapacitive coupling: Capacitance

Data Source

PatentUS12150303B2Integrated assemblies having charge-trapping material arranged in vertically-spaced segments, and methods of forming integrated assemblies
Publication Date: 2024.11.19 LODESTAR LICENSING GROUP LLC
  • US12150303B2 patent drawing
  • US12150303B2 patent drawing
  • US12150303B2 patent drawing

AI summary

Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.