Segmented Charge-Trapping Material in 3D NAND Memory Arrays

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Solution Overview

Problem

Conventional three-dimensional NAND memory arrays face data retention issues due to charge migration between memory cells, caused by continuous charge-trapping material extending across multiple cells.

Innovation Solution

Incorporating breaks in the charge-trapping material between memory cells, with vertically stacked segments of charge-trapping material and charge-tunneling material, and using charge-blocking and insulative materials to prevent charge migration, forming a segmented structure that impedes charge migration between cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If continuous charge-trapping material is used across multiple memory cells, then manufacturing simplicity is maintained, but charge migration between cells occurs causing data retention issues

Engineering Contradiction:
Improvedata retentionVSAvoidcharge-trapping material structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The charge-trapping material is divided into multiple discrete segments positioned at different vertical levels within the memory cell stack. Each segment is separated by intervening dielectric material, creating isolated charge trapping regions that prevent charge migration between cells while maintaining effective data storage capability.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If charge-trapping material extends across multiple memory cells, then manufacturing process is simplified, but charge migration between adjacent cells is enabled

Engineering Contradiction:
Improvecharge-trapping material depositionVSAvoidcharge migration
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The charge-trapping material is segmented into discrete portions at different vertical levels, with dielectric material positioned between segments to electrically isolate them. This segmentation prevents charge migration between adjacent memory cells while still allowing straightforward deposition processes to be used.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Intervening dielectric material is introduced between segments of charge-trapping material to act as an electrical barrier. This dielectric intermediary prevents charge carriers from migrating between adjacent memory cells through the charge-trapping material, eliminating the harmful charge migration effect.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If vertically stacked memory cells are used, then storage density is improved, but charge migration paths between cells increase

Engineering Contradiction:
Improvestorage capacityVSAvoidcharge isolation
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The charge-trapping material is segmented into multiple discrete segments positioned at different vertical levels within the stacked memory cell structure. Each segment is electrically isolated from others by intervening dielectric material, preventing charge migration paths between adjacent memory cells while maintaining high storage density through the vertical stacking architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the charge-trapping material are given different spatial positions at various vertical levels, with dielectric material strategically placed between segments. This local differentiation creates electrically isolated zones that prevent charge migration while preserving the high-density three-dimensional memory structure.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10541252B2Memory arrays, and methods of forming memory arrays
Publication Date: 2020.01.21 MICRON TECHNOLOGY INC
  • US10541252B2 patent drawing
  • US10541252B2 patent drawing
  • US10541252B2 patent drawing

AI summary

Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.