Segmented ESD Protection Circuit for IC Pin Loading
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Solution Overview
Problem
Integrated circuits face challenges in ESD protection, particularly with smaller feature sizes, where large ESD devices load pins, reduce performance, and consume significant area, making it difficult to design reusable circuits that effectively manage ESD events like CDM and HBM.
Innovation Solution
The proposed solution involves an integrated circuit design with a circuit block that includes separate ESD protection circuits for the pad and the IC, sized for specific current requirements, using diodes and ESD power clamps to manage ESD events, and a virtual pad configuration that reduces load on pins, allowing for more efficient ESD protection without impacting performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large ESD devices are used to protect against ESD events, then ESD protection capability is improved, but pin loading increases and performance deteriorates
Solution Approach 1:
The ESD protection function is segmented into two separate circuits: a first ESD protection circuit within the circuit block sized for internal current, and a second ESD protection circuit at the IC level sized for total IC current. This segmentation allows each circuit to be optimally sized for its specific purpose, reducing the loading on pins while maintaining comprehensive ESD protection capability.
2Reliability
If large ESD devices are used to protect against ESD events, then ESD protection capability is improved, but area consumption increases
Solution Approach 1:
By segmenting the ESD protection into two circuits with different sizing requirements, the total area consumption is reduced. The first ESD protection circuit uses smaller devices sized only for internal block current, while the second circuit handles the remaining protection needs, optimizing the overall area utilization compared to a single large ESD protection circuit.
3Reliability
If ESD devices are sized for complete IC current, then ESD protection is improved, but circuit block reuse becomes difficult
Solution Approach 1:
The ESD protection is divided such that the first ESD protection circuit in the circuit block is sized only for the current that may be sourced within that block. This allows the circuit block to be reused in different IC designs without requiring changes to the ESD protection sizing, while the second ESD protection circuit at the IC level provides the additional protection needed for the complete IC current.
Solution Approach 2:
The first ESD protection circuit is designed with universal sizing that can be applied across multiple circuit block instances and different IC designs. By sizing it only for internal block current rather than total IC current, it becomes a reusable component that maintains ESD protection capability while adapting to different IC configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides robust ESD protection with reduced loading on pins, improving the reuse of circuit blocks in different IC designs and maintaining performance, while effectively managing ESD events by distributing current and voltage safely across the IC and its package.
Implementation Method 1
The diodes and other protection circuits are designed to turn on if an ESD event occurs, rapidly discharging the ESD event to avoid damage to the functional circuits
Data Source
AI summary
In an embodiment, an integrated circuit (IC) may include a circuit block that couples to one or more pins of the IC to communicate and/or receive power on the pins. The circuit block may include a ground connection, which may be electrically insulated/electrically separate from the ground connection of other components of the integrated circuit. In an embodiment, the circuit block may include an ESD protection circuit for the pad coupled to the pin. The IC may include another ESD protection circuit for the pad. The circuit block's ESD protection circuit may be sized for the current that may produced within the circuit block for an ESD event, and the IC's ESD protection circuit may be sized for the current that may be produced from the other components of the IC.