Segmented Filament Storage Element for Multi-State Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices with electric fuses face challenges in increasing memory cell capacity while maintaining a compact size, as they require large currents to break filaments, leading to increased memory cell size and chip size.
Innovation Solution
A semiconductor device with a storage element comprising a filament with a first conductive layer, a second conductive layer, and an insulation layer, capable of achieving three identifiable resistance states by changing the combination of these layers' states, and a writing unit that applies a blow current to produce these states, reducing the current required for filament breaking and allowing for more efficient memory cell capacity without increasing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional electric fuse uses a filament that requires large current to break, then the filament can achieve binary information storage, but the memory cell size increases
Solution Approach 1:
The filament is segmented into multiple conductive layers (first conductive layer, second conductive layer, and intermediate layer) separated by insulation layers. This segmentation allows the filament to achieve multiple resistance states (at least three identifiable states) by selectively changing the conductivity of different layers, enabling multi-level information storage without increasing memory cell size
Solution Approach 2:
The invention changes the resistance parameter of the filament by applying blow currents that selectively modify the conductivity of different conductive layers. By controlling the blow current magnitude and duration, the system can transition the filament between multiple resistance states (R0, R1, R2, etc.), achieving multi-level storage while maintaining compact cell dimensions
2Productivity
If the memory cell capacity is increased to store more information, then the storage element needs to handle more data, but the chip size increases
Solution Approach 1:
The invention transitions from binary storage (0 or 1) to multi-level storage by adding a resistance dimension. The filament can occupy at least three identifiable resistance states, allowing each memory cell to store multiple bits of information (e.g., 2 bits per cell for 4 states, or more for additional states). This dimensional expansion in resistance space enables increased memory capacity without proportionally increasing chip area
3Area of moving object
If a smaller current is used to break the filament, then the transistor size can be reduced, but the filament breaking capability is compromised
Solution Approach 1:
The filament structure with multiple conductive layers and insulation layers enables progressive modification. Smaller blow currents can selectively change the resistance of individual layers without completely breaking the filament, achieving multi-state storage. Larger currents can be applied when needed to achieve complete breakdown. This segmented structure allows the use of smaller transistors that can only provide limited current, while still maintaining full filament breaking capability when required
Solution Approach 2:
The invention employs partial action by applying blow currents that are sufficient to modify certain conductive layers but not necessarily to completely break the filament. This allows for incremental resistance changes that create multiple stable states. The filament breaking capability is preserved as a subset of these states (complete breakdown represents one of the high-resistance states), enabling smaller transistors to perform both partial modification and complete breaking functions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a significant increase in memory cell capacity per unit area, reducing the size of memory cells and peripheral circuits, while maintaining compatibility with conventional manufacturing processes, thus avoiding cost increases and simplifying circuit layouts.
Implementation Method 1
The filament obtains at least three identifiable resistance states by changing a combination of a state of the first conductive layer, a state of the second conductive layer, and a state of the insulation layer
Implementation Method 2
a insulation layer... with at least the insulation layer interposed between the first conductive layer and the second conductive layer
Data Source
AI summary
A semiconductor device capable of efficiently increasing a capacity of a mounted storage element while achieving space saving, and an electronic apparatus including this semiconductor device are provided. The semiconductor device includes a storage element including a filament that has a first conductive layer, a second conductive layer, and an insulation layer. The first conductive layer and the second conductive layer are stacked with at least the insulation layer interposed between the first conductive layer and the second conductive layer. The filament obtains at least three identifiable resistance states by changing a combination of a state of the first conductive layer, a state of the second conductive layer, and a state of the insulation layer. The semiconductor device further includes a writing unit that produces the at least three identifiable resistance states by applying a blow current to the storage element.