Segmented Gate Driving Circuit for Peak Current Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional gate driving circuits in active matrix display devices experience high peak currents and power loss due to periodic variations in the modulated gate power supply voltage, leading to potential circuit burnout.
Innovation Solution
The gate driving circuit is designed with multiple independent gate signal generating modules, each equipped with a voltage modulation circuit and a gate output buffer circuit, which modulate the external gate power supply voltage using internal shift data signals to reduce peak currents by enabling parallel-coupled output stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single pulse width modulation circuit is used to provide modulated voltage signal to multiple cascade-connected gate driver integrated circuits, then the circuit complexity is reduced, but high peak current occurs when the potential is retrieved to the gate power supply voltage
Solution Approach 1:
The gate driving circuit is divided into multiple independent gate signal generating modules, where each module includes its own voltage modulation circuit. This segmentation allows each module to independently modulate the gate power supply voltage, avoiding the high peak current issue that occurs when a single modulation circuit serves multiple cascade-connected drivers.
2Stability of the object's composition
If the potential of modulated voltage signal is periodically varied to achieve waveform uniformity, then even display effect is improved, but high peak current occurs during potential retrieval
Solution Approach 1:
By segmenting the gate driving circuit into independent modules with separate voltage modulation circuits, each module can maintain waveform uniformity for its output without causing high peak currents that would compromise circuit reliability. The independence of each module prevents the harmful interaction that occurs in cascade-connected configurations.
Solution Approach 2:
Each gate signal generating module acts as an intermediary between the gate power supply voltage and the gate driver integrated circuits. The voltage modulation circuit within each module modulates the power supply voltage locally, serving as a mediator that prevents high peak currents from reaching the output stage while maintaining the necessary waveform characteristics.
3Area of stationary object
If cascade-connected gate driver integrated circuits are used, then the gate driving circuit can cover larger display areas, but high peak current occurs due to shared modulation circuit
Solution Approach 1:
Instead of using cascade-connected gate driver integrated circuits that share a common voltage modulation circuit, the invention segments the system into independent gate signal generating modules. Each module has its own voltage modulation circuit, allowing the system to cover large display areas without the harmful high peak current effects that arise from shared modulation resources.
Data Source
AI summary
An exemplary gate driving circuit is adapted for receiving an external gate power supply voltage and an external control signal, sequentially generating multiple internal shift data signal groups and thereby sequentially outputting multiple gate signals. Each of the internal shift data signal groups includes multiple sequentially-generated internal shift data signals. The gate driving circuit includes multiple gate signal generating modules. Each of the gate signal generating modules includes a voltage modulation circuit and a gate output buffer circuit. The voltage modulation circuit modulates the external gate power supply voltage according to a corresponding one of the internal shift data signal groups and the external control signal, and thereby a modulated voltage signal is obtained. The gate output buffer circuit includes a plurality of parallel-coupled output stages. The output stages output the modulated voltage signal as a part of the gate signals during the output stages being sequentially enabled.