Segmented Gate Electrode Parasitic Capacitance Reduction
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Solution Overview
Problem
In semiconductor devices like IGBTs, parasitic capacitance between the emitter, collector, and gate electrodes affects switching rate and switching losses, requiring a reduction in parasitic capacitance to improve switching characteristics.
Innovation Solution
The semiconductor device features a gate electrode with varying lengths, where a shorter gate electrode length is used in regions between emitter regions, reducing parasitic capacitance without significantly impacting current flow, thereby enhancing switching performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the gate electrode length is increased to improve current flow, then the current carrying capacity is improved, but the parasitic capacitance increases worsening switching characteristics
Solution Approach 1:
The gate electrode is divided into multiple sections with different lengths along the channel direction. The first gate electrode has a first length, the second gate electrode has a second length shorter than the first, and the third gate electrode has a third length longer than the second. This segmentation allows different portions of the gate electrode to have optimized lengths for their specific functions, reducing overall parasitic capacitance while maintaining current carrying capacity.
Solution Approach 2:
Different sections of the gate electrode are given different local properties (different lengths) to optimize performance in specific regions. The varying gate lengths create localized electric field distributions that reduce parasitic capacitance in critical areas while maintaining adequate current flow in other regions.
2Loss of energy
If the gate electrode length is decreased to reduce parasitic capacitance, then switching characteristics are improved, but the current flow capability deteriorates
Solution Approach 1:
Instead of uniformly shortening the gate electrode, it is segmented into sections with progressively varying lengths. This allows the gate electrode to have shorter effective length in regions where parasitic capacitance is critical, while maintaining longer effective length in regions needed for current carrying, thus resolving the contradiction between reducing capacitance and maintaining power capability.
Solution Approach 2:
The gate electrode length parameter is changed progressively across different sections rather than being uniform. The first length, second length, and third length form a gradient that optimizes the balance between parasitic capacitance reduction and current carrying capacity maintenance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance, improving switching characteristics and preventing IGBT breakdown by limiting current flow and reducing switching losses.
Implementation Method 1
parasitic capacitance is generated between the emitter potential electrode, the collector potential electrode, and the gate potential electrode
Data Source
AI summary
The semiconductor device includes, in plan view, a gate electrode having a first portion located on a side surface portion where a plurality of emitter regions are formed, and a gate electrode having a second portion located between the plurality of emitter regions. The second portion of the gate electrode has a length shorter than first portion in the direction from the main surface to the back surface of the gate electrode of the semiconductor substrate.