Segmented Gate Isolation Structure for Leakage-Safe Scaling
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Solution Overview
Problem
Existing multi-gate devices, such as FinFETs and gate-all-around transistors, face challenges in achieving the required device density and performance as gate pitch decreases, leading to issues like current leakage and photoresist defects during fabrication.
Innovation Solution
The formation of isolation structures with varying widths and arrangements in gate structures, including wide and narrow segments, to ensure effective electrical isolation and prevent photoresist defects during the patterning process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous poly on diffusion edge (CPODE) or diffusion edge poly (PODE) patterns are used to avoid leakage between neighboring devices, then device leakage is reduced, but device density and cell isolation are insufficient at scaled dimensions
Solution Approach 1:
The gate structure is segmented into multiple sections with alternating isolated and non-isolated regions. The isolation structures divide the gate into discrete segments, allowing selective electrical isolation between adjacent active regions while maintaining overall device density. This segmentation enables the poly gate to provide both leakage prevention and high density by creating controlled isolation zones.
Solution Approach 2:
The gate structure implements local quality variations through alternating isolated and non-isolated sections. Different portions of the gate have different electrical isolation properties: some sections provide strong isolation to prevent leakage, while other sections maintain continuity for optimal device performance. This local differentiation allows the structure to simultaneously address leakage prevention and density requirements.
2Productivity
If gate pitch is reduced to increase device density, then device density increases, but current leakage and photoresist defects increase
Solution Approach 1:
By segmenting the gate into isolated and non-isolated sections, the structure prevents current leakage paths that would otherwise form in continuously scaled-down gates. The isolation structures create electrical barriers between adjacent devices even as the overall gate pitch decreases, maintaining reliability while enabling higher density.
Solution Approach 2:
The isolation structures act as intermediary elements between adjacent active regions. These intermediate features provide electrical isolation without requiring large spacing between devices, enabling the gate pitch to be reduced while maintaining reliable current confinement. The isolation structures mediate between the competing requirements of high density and low leakage.
3Productivity
If gate pitch is reduced to increase device density, then device density increases, but photoresist defects occur during patterning
Solution Approach 1:
The segmented gate structure with alternating isolated and non-isolated sections creates a patterning design that avoids the photoresist defects associated with continuous fine-pitch patterns. The isolation structures provide natural break points and spacing variations that improve photoresist performance during patterning, reducing defects while maintaining high device density.
4Reliability
If isolation structures with varying widths are formed in gate structures, then electrical isolation and etch depth are improved, but device complexity increases
Solution Approach 1:
The gate structure implements local quality variations through alternating isolated and non-isolated sections. Different portions of the gate have different electrical isolation properties: some sections provide strong isolation to prevent leakage, while other sections maintain continuity for optimal device performance. This local differentiation allows the structure to simultaneously address leakage prevention and density requirements.
Data Source
AI summary
Embodiments of present disclosure relates to forming isolation structures in gate structures to prevent current leakage through source/drain regions (EPI), transistors, and silicon substrate. The isolation structures may be formed in the gate structure prior to or after the replacement gate sequence.