Segmented Giga Interposer Layout for Low-Warpage CoWoS Packaging

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The challenge in semiconductor packaging is the warpage and stress issues in large interposers due to increased integration density, leading to difficulties in bonding with substrates and risks of cracking or delamination.

Innovation Solution

The use of multiple smaller interposers instead of a single large interposer, with dies bonded to both interposers, reduces warpage and stress, allowing easier bonding to a substrate while maintaining planarity and reducing the risk of cracking or delamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a single large interposer is used to achieve high integration density, then the integration density is improved, but warpage and stress issues occur leading to bonding difficulties and cracking risks

Engineering Contradiction:

Improveintegration densityVSAvoidbonding reliability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent divides a single large interposer into multiple smaller interposers arranged in an array. Each smaller interposer carries a portion of the semiconductor dies, thereby maintaining high integration density while reducing the size of individual interposers to minimize warpage and stress. This segmentation resolves the contradiction by distributing the integration load across multiple smaller units rather than concentrating it in one large interposer.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If a single large interposer is used to increase integration density, then more dies can be mounted, but the interposer experiences warpage and stress leading to cracking or delamination

Engineering Contradiction:

Improvenumber of diesVSAvoidinterposer strength

Core Design Contradiction:

Quantity of substanceVSStrength

Solution Approach 1:

The interposer structure is segmented into multiple smaller interposers that are laterally adjacent and spaced apart. Each smaller interposer has reduced dimensions that prevent excessive warpage and stress accumulation. The array configuration allows a large number of dies to be mounted across multiple interposers while each individual interposer maintains sufficient strength and structural integrity.

Inventive Principle:

Principle #1Segmentation

3Ease of manufacture

If multiple smaller interposers are used instead of a single large interposer, then warpage and stress are reduced improving bonding ease, but the device structure becomes more complex

Engineering Contradiction:

Improvebonding easeVSAvoidinterposer structure complexity

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent employs multiple smaller interposers arranged in a regular array pattern with consistent spacing. While this segmentation improves bonding ease by reducing warpage and stress on each individual interposer, the regular and systematic arrangement minimizes the increase in structural complexity. The modular nature of the array allows for standardized manufacturing processes and simplifies the overall fabrication workflow compared to a custom single-large-interposer design.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS20260076277A1Giga interposer integration through chip-on-wafer-on-substrate

Publication Date: 2026.03.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.