Segmented Semiconductor Interconnects to Prevent Via Fill Voids
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Solution Overview
Problem
Increasing transistor density and decreasing device features in semiconductor manufacturing introduce manufacturing defects that affect device performance and functionality, particularly due to high-aspect ratio monolithic vias leading to fill errors and void formation.
Innovation Solution
Implementing a spatially-efficient interconnect structure with bridge pillars that electrically connect circuit elements across a base isolation layer, reducing die size and enabling more compact routing of power and signals through segmented interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-aspect ratio monolithic vias are used to connect circuit elements, then vertical connectivity is achieved, but fill errors and void formation occur during manufacturing
Solution Approach 1:
The via structure is divided into multiple segments (first via segment, second via segment, and bridge pillar) rather than using a single monolithic via. This segmentation allows each portion to be formed and filled separately, eliminating the fill errors and voids that occur in high-aspect ratio monolithic vias while maintaining vertical connectivity through the base isolation layer.
2Productivity
If transistor dimensions are decreased to increase density, then device capacity increases, but manufacturing defects have larger influence on performance
Solution Approach 1:
By segmenting the interconnect structure into multiple portions that can be formed and filled separately, the invention reduces manufacturing variability and defect impact on individual transistors. This allows for higher transistor density while maintaining performance stability, as defects in one segment do not propagate through the entire structure.
3Ease of manufacture
If conventional monolithic vias are used, then manufacturing process is simple, but parasitic capacitance is high and switching speed is limited
Solution Approach 1:
The segmented via structure with bridge pillars reduces parasitic capacitance by optimizing the distribution of conductive material and reducing via resistance. Although the structure is more complex, it enables faster switching speeds while the manufacturing process remains compatible with existing semiconductor fabrication techniques.
4Speed
If segmented interconnect structure is implemented, then parasitic capacitance is reduced and switching speed increases, but device complexity increases
Solution Approach 1:
The bridge pillar extends in the vertical dimension through the base isolation layer, connecting the first and second via segments. This vertical arrangement optimizes space utilization and reduces parasitic capacitance while maintaining a relatively compact lateral footprint, balancing performance improvement with structural complexity.
Data Source
AI summary
A device includes: a first transistor on a first side of an isolation layer and having a first S/D electrode; a second transistor on a second side of the isolation layer and having a second S/D electrode; a conductive layer, the second transistor being between the first transistor and conductive layer; and a first via extending through the isolation layer and coupling the first S/D electrode to a conductive line of the conductive layer, the first via including: a first segment overlapped on a first side by the first S/D electrode and overlapped on a second side by the first conductive line; and a second segment connected on a first side to the first S/D electrode and connected on a second side to the first segment, the second segment being at least partially in the isolation layer, and the first segment and second S/D electrode having a same height.