Segmented Isolation Capacitor Layout for High-Voltage IC Feedback
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Solution Overview
Problem
Conventional high voltage isolation (ISO) capacitors in integrated circuits (ICs) require multiple large capacitors in series, occupying significant die area and potentially degrading performance, especially in applications with high voltage and feedback loops.
Innovation Solution
The introduction of a segmented ISO capacitor with a bottom plate comprising multiple electrically isolated segments, allowing for reduced die area and maintaining performance by providing separate feedback paths without measurable degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If multiple large capacitors are used in series for high voltage isolation, then breakdown voltage is improved, but die area is increased
Solution Approach 1:
The bottom plate of the ISO capacitor is divided into multiple electrically isolated segments. This segmentation allows the capacitor to achieve high breakdown voltage through the series connection of multiple dielectric layers while maintaining a compact structure that reduces overall die area compared to using multiple separate large capacitors.
Solution Approach 2:
Multiple dielectric layers are stacked vertically to form a nested structure where each layer contributes to the overall breakdown voltage. The segmented bottom plate is positioned beneath these stacked dielectric layers, creating a compact vertical arrangement that achieves high voltage isolation without proportionally increasing die area.
2Reliability
If multiple large capacitors are used in series for high voltage isolation, then isolation performance is improved, but device complexity is increased
Solution Approach 1:
The bottom plate is segmented into multiple electrically isolated sections, with each segment connected to different voltage potentials. This segmentation enables the single capacitor structure to provide multiple isolation functions that would otherwise require multiple separate capacitors, thereby improving isolation performance while reducing device complexity.
Solution Approach 2:
The segmented bottom plate structure serves multiple functions simultaneously: it provides high voltage isolation, enables feedback loops, and supports multiple dielectric layers. This multi-functionality allows a single capacitor structure to replace what would traditionally require multiple separate components, reducing overall device complexity.
3Ease of manufacture
If conventional ISO capacitor structure is used, then manufacturing is simplified, but feedback loop efficiency is degraded
Solution Approach 1:
The segmented bottom plate provides separate access points for feedback signals while maintaining compatibility with standard semiconductor fabrication processes. Each segment can be independently connected to feedback circuitry, enabling efficient feedback loops without requiring complex additional manufacturing steps.
Solution Approach 2:
The segmentation of the bottom plate introduces a new dimensional aspect to the capacitor structure, allowing feedback paths to be established in the planar direction rather than requiring vertical stacking. This enables efficient feedback loops while maintaining manufacturing simplicity through standard photolithography and metallization processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The segmented ISO capacitor reduces die area requirements while maintaining breakdown voltage and enabling efficient feedback loops, enhancing IC performance and efficiency.
Implementation Method 1
The ISO device accomplishes this function using an ISO barrier that has a high breakdown voltage and low leakage. A highly resistive path generally exists across the ISO barrier, but the device can still transfer information in the desired AC signal across the ISO barrier by capacitive, inductive, or optical coupling techniques.
Implementation Method 2
Capacitive HV ISO devices primarily use silicon-dioxide (SiO2) capacitors to provide the isolation. With a dielectric strength of about 300 to 800 V/μm, SiO2 has the highest dielectric strength among commonly used HV ISO dielectric materials.
Data Source
AI summary
An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.