Segmented LED Chip Layout for High-PPI Small-Current Displays
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Solution Overview
Problem
Existing light-emitting diode (LED) chip manufacturing processes face challenges in achieving high pixels per inch (PPI), difficulty in reducing chip size, high manufacturing costs, low yield, and inefficient luminance control under small currents, especially for chips smaller than 3*5 mil.
Innovation Solution
The LED chip design includes a first conductive type semiconductor layer, a light-emitting layer, and at least two second conductive type semiconductor layers with spaced-apart electrodes, allowing for multiple independent light-emitting structures within a single chip, enabling smaller sizes and higher PPI while maintaining efficiency under small currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the chip size is reduced to achieve higher pixels per inch, then the PPI is improved, but the manufacturing yield decreases and costs increase
Solution Approach 1:
The patent divides a single large chip into multiple smaller light-emitting structures (first, second, and third light-emitting structures) on one chip substrate. This segmentation allows each structure to be small enough for high PPI while the overall chip remains large enough for acceptable manufacturing yield. The chip is further divided into multiple chips through dicing, creating a hierarchical segmentation that resolves the contradiction between small feature size and manufacturing yield.
2Manufacturing precision
If the chip size is reduced to achieve higher pixels per inch, then the PPI is improved, but the manufacturing cost increases
Solution Approach 1:
The patent merges multiple light-emitting structures onto a single chip substrate, allowing them to share common manufacturing processes and reducing per-unit costs. The first, second, and third light-emitting structures are formed on the same chip through integrated fabrication steps, and the chip is then diced into multiple smaller chips, spreading the manufacturing cost across multiple sellable units rather than requiring separate fabrication for each small chip.
3Manufacturing precision
If the chip size is reduced below 3*5 mil, then the PPI is improved, but the luminance control efficiency under small currents deteriorates
Solution Approach 1:
The patent segments the chip into multiple independent light-emitting structures, each capable of being controlled by separate pixel circuits. This allows each small structure to be optimized for its specific function while the collective arrangement maintains overall efficiency. The segmentation enables precise control of each sub-pixel region, improving luminance control efficiency even at small sizes by allowing independent current control for each light-emitting structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design facilitates the production of smaller, more efficient LED chips with improved yield and reduced costs, enabling higher PPI and enhanced luminance control, particularly under small current drives.
Implementation Method 1
Light-emitting diode (LED) is a semiconductor device that emits light by recombination of electrons and holes
Data Source
AI summary
A light-emitting diode chip, a display substrate and a manufacturing method thereof are disclosed. The light-emitting diode chip includes a first conductive type semiconductor layer, a light-emitting layer, at least two second conductive type semiconductor layers, and at least two first electrodes; the at least two second conductive type semiconductor layers are at a side of the light-emitting layer away from the first conductive type semiconductor layer, the at least two first electrodes are electrically respectively connected with the at least two second conductive type semiconductor layers. Orthographic projections of the at least two second conductive type semiconductor layers on the first conductive type semiconductor layer are spaced apart from each other, and orthographic projections of the at least two first electrodes on the first conductive type semiconductor layer are spaced apart from each other.