Segmented Multiplier Circuit for Low-Area Neural MAC Units
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Solution Overview
Problem
Conventional multipliers and multiply-accumulate circuits in neural network processors face challenges with high power consumption and large chip area due to the large number of multipliers required for convolution operations, which are critical for efficient neural network processing.
Innovation Solution
A novel multiplier design incorporating selection circuits and partial product summing circuits, along with compression tree circuits, reduces the number of operations and partial products, thereby decreasing chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional multipliers and multiply-accumulate circuits are used for convolution operations in neural network processors, then the multiplication and accumulation operations can be completed, but the chip area becomes large and power consumption increases
Solution Approach 1:
The second operand is divided into one or more third operands by bit, and the multiplication is performed segment by segment. The selection circuit selects preset multiples of the first operand based on each third operand, avoiding the need for a complete traditional multiplier structure. This segmentation approach significantly reduces chip area while maintaining convolution operation efficiency.
Solution Approach 2:
Preset multiples of the first operand are pre-calculated and stored in the selection circuit. During multiplication, the selection circuit directly selects the required preset multiple based on the third operand, eliminating the need for real-time calculation of all partial products. This preliminary action reduces the complexity and area of the multiplier circuit.
2Productivity
If conventional multipliers and multiply-accumulate circuits are used for convolution operations in neural network processors, then the multiplication and accumulation operations can be completed, but power consumption becomes high
Solution Approach 1:
The multiplication operation is segmented into multiple selection operations on preset multiples rather than a complete multiplication process. The selection circuit only activates the necessary logic paths based on the third operand, reducing dynamic power consumption compared to conventional multipliers that must always be ready to perform full multiplication.
Solution Approach 2:
The selection circuit can select from multiple preset multiples of the first operand, making it a multi-functional component that handles different multiplication cases (0×, 1×, 2×, 3×, etc.) with a single circuit structure. This universality reduces the overall circuit complexity and power consumption compared to having separate circuits for each multiplication case.
3Area of stationary object
If the number of multipliers is reduced to decrease chip area, then chip area is reduced, but the complexity of each multiplier increases
Solution Approach 1:
Preset multiples of the first operand are pre-calculated and stored in the selection circuit before the multiplication operation. This preliminary action moves the computational complexity from the runtime multiplication process to the initialization phase, allowing the runtime circuit to simply select from pre-computed values, thereby reducing the complexity of the active multiplier circuit.
Solution Approach 2:
The selection circuit acts as an intermediary between the first operand and the partial product summing circuit. Instead of directly computing all partial products, the selection circuit mediates by selecting the appropriate preset multiple based on the third operand, simplifying the overall circuit structure and reducing complexity.
Data Source
AI summary
The present disclosure relates to a multiplier, a multiply-accumulate circuit, and a convolution operation unit. The multiplier includes: one or more selection circuits, each of the one or more selection circuits respectively configured to select a target preset multiple of a first operand from a preset multiple of a first operand as a fourth operand according to a corresponding third operand, wherein the target preset multiple is equal to a value of the third operand; and a partial product summing circuit, each of one or more input terminals of the partial product summing circuit respectively connected to an output terminal of corresponding one of at least one or more selection circuits, wherein the partial product summing circuit is configured to calculate a partial product sum of one or more fourth operands from the one or more selection circuits.