Segmented Lower Pad Structure for Warpage-Resistant Chip Stacking
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Solution Overview
Problem
Existing semiconductor packages face challenges in enhancing reliability and durability, particularly in the electrical connections between semiconductor chips, which can lead to non-wet failure due to warpage and inadequate contact between connection terminals.
Innovation Solution
The semiconductor package design includes a first semiconductor chip with a through via and a lower pad featuring a segmented structure, where a second segment surrounds the upper pad, and a connection terminal that covers the lateral surface, ensuring a secure electrical connection through a U-shaped configuration, thereby enhancing adhesion and reducing thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional pad structure is used without surrounding the upper pad, then the manufacturing process is simpler, but non-wet failure occurs due to warpage and inadequate contact between connection terminals
Solution Approach 1:
The lower pad is divided into two segments: a first segment positioned at the bottom and a second segment positioned at the top. This segmentation allows the lower pad to independently contact the connection terminal and surround the upper pad, ensuring reliable electrical connection while accommodating warpage without requiring a completely different pad structure
Solution Approach 2:
The second segment of the lower pad is positioned to surround the upper pad, creating a nested configuration where the lower pad structure encompasses the upper pad. This nesting ensures that even when warpage occurs, the connection terminal maintains adequate contact with the lower pad through the surrounding structure
2Reliability
If the lower pad is designed to surround the upper pad completely, then electrical connectivity is maintained under warpage, but the device complexity increases
Solution Approach 1:
The lower pad is segmented into two distinct parts positioned at different heights, allowing selective surrounding of the upper pad only where necessary for reliability, rather than complete surrounding that would increase complexity unnecessarily
Solution Approach 2:
The surrounding function is applied locally at the top segment rather than uniformly across the entire lower pad structure, providing reliability where needed while maintaining simplicity in other areas
Data Source
AI summary
A semiconductor package includes a second semiconductor chip disposed on a first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate, a through via, and a lower pad disposed on the through via. The lower pad includes a first segment and a second segment connected thereto. The first segment overlaps the through via. The second segment is disposed on an edge region of the first segment. The second segment has an annular shape. The second semiconductor chip includes a second semiconductor substrate, an upper pad disposed on a bottom surface of the second semiconductor substrate, and a connection terminal disposed between the upper and lower pads. The second segment at least partially surrounds a lateral surface of the upper pad. A level of a top surface of the second segment is higher than that of an uppermost portion of the connection terminal.