Select Gate Erase Bias Adjustment Across Memory Erase Loops
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Solution Overview
Problem
The challenge of erase operation failures in memory devices due to increased trap-up at select gates (SGS0) during program/erase cycles, leading to resistance issues and reduced endurance performance, is addressed by implementing an erase pulse loop dependent adjustment of select gate erase bias voltage.
Innovation Solution
The erase operation involves a series of loops with adjustable erase bias voltage levels applied to the first and second select gates (SGS0 and SGS1), where the bias voltage is reduced in subsequent loops to minimize trap-up and prevent erase failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a constant erase bias voltage is applied to select gates during all erase loops, then the erase operation structure is simple, but trap-up at select gates increases leading to erase failures and reduced endurance
Solution Approach 1:
The patent applies dynamics by transitioning from a static constant erase bias voltage to a dynamic loop-dependent erase bias voltage that changes across different erase loops. The erase bias voltage is adjusted based on the current erase loop number, allowing the system to adapt to changing trap-up conditions and maintain reliable erase operations throughout multiple loops.
Solution Approach 2:
The patent implements parameter changes by modifying the erase bias voltage parameter across different erase loops. Specifically, the erase bias voltage is set to different values depending on the loop number, with higher voltages applied in earlier loops when trap-up is more severe, and reduced voltages in later loops, thereby optimizing erase effectiveness while preventing erase failures.
2Reliability
If high erase bias voltage is applied to select gates throughout all erase loops, then erase operation effectiveness is maintained, but trap-up at select gates increases causing resistance issues and endurance degradation
Solution Approach 1:
The patent applies periodic action by implementing a structured sequence of erase loops with varying bias voltages. Instead of applying continuous high voltage, the system uses periodic erase pulses with loop-dependent voltage levels, where the voltage pattern repeats across loops but with progressive adjustment, effectively managing trap-up while maintaining erase effectiveness over time.
Solution Approach 2:
The patent applies partial action by using different erase bias voltage levels for different erase loops rather than applying maximum voltage throughout. In later erase loops where trap-up is less severe, reduced voltage levels are sufficient to complete the erase operation, thereby avoiding the excessive voltage that would cause additional trap-up and endurance degradation.
Data Source
AI summary
Control logic of a memory device to initiate an erase operation including a set of erase loops to erase one or more memory cells of the memory device. During a first erase loop of the set of erase loops, a first erase pulse having an erase voltage level is caused to be applied to a source line associated with the one or more memory cells. During the first erase loop, a first erase bias voltage having an initial voltage level is caused to be applied to a first select gate and a second erase bias voltage having the initial voltage level is caused to be applied to a second select gate associated with the source line, where the first erase bias voltage level is based on a first delta voltage level. During a subset of erase loops following the first erase loop, a second erase pulse having the erase voltage level is caused to be applied to the source line. During the subset of erase loops, a first adjusted erase bias voltage is caused to be applied to the first select gate and a second adjusted erase bias voltage is caused to be applied to the second select gate.