Select Transistor Gate Structure for NAND Flash Memory
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Solution Overview
Problem
Current stacking-type NAND flash memory devices face challenges in achieving excellent cutoff characteristics for select transistors while maintaining low manufacturing costs and power consumption, and simplifying manufacturing processes.
Innovation Solution
The design incorporates select transistors with charge storage layers, allowing for threshold voltage adjustments through a control circuit that manages the state of memory strings, bit lines, and source lines, enabling efficient write, read, and erase operations while curbing manufacturing costs and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If select transistors are designed with conventional structures in stacking-type NAND flash memory, then manufacturing processes can be simplified, but cutoff characteristics deteriorate
Solution Approach 1:
The select transistor gate is formed by nesting multiple conductive layers (first conductive layer and second conductive layer) together, creating a multi-layer gate structure. This nested configuration increases the effective gate width without adding lateral space, thereby improving cutoff characteristics while maintaining compatibility with existing manufacturing processes
Solution Approach 2:
The invention transitions from a conventional single-layer gate structure to a multi-layer vertical gate structure. By stacking conductive layers in the vertical dimension, the gate width is effectively increased without expanding the lateral footprint, thus improving transistor performance while maintaining planar manufacturing simplicity
2Reliability
If select transistors are designed to achieve excellent cutoff characteristics, then reliability improves, but device complexity increases
Solution Approach 1:
Multiple conductive layers that would otherwise be separate structures are merged and connected to form a unified multi-layer gate. This merging approach achieves enhanced cutoff characteristics through increased effective gate width while avoiding the complexity of multiple independently controlled gates, as all layers work together as a single gate structure
3Device complexity
If conventional select transistors are used in stacking-type NAND flash memory, then device complexity is reduced, but power consumption increases
Solution Approach 1:
The nested multi-layer gate structure increases the effective gate width, which improves the transistor's ability to control current flow. This enhanced control capability reduces leakage current when the transistor is in the off state, thereby lowering power consumption without significantly increasing device complexity
Solution Approach 2:
By increasing the gate width in the vertical dimension through layer stacking, the transistor achieves better channel control. This improved control reduces unwanted current leakage and lowers power consumption while maintaining a compact lateral footprint and relatively simple device architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in select transistors with improved cutoff characteristics, reduced manufacturing costs, and simplified control operations, effectively addressing the limitations of existing technologies.
Implementation Method 1
select transistors with charge storage layers, allowing for threshold voltage adjustments
Data Source
AI summary
According to one embodiment, in the case of performing an operation for increasing a threshold voltage of a first transistor or a third transistor, a control circuit is configured to apply a first voltage to a bit line, and apply a second voltage greater than the first voltage to a gate of a second transistor, thereby rendering the second transistor in a conductive state to transfer the first voltage to a second semiconductor layer, and then apply a program voltage to a gate of the first transistor or the third transistor to store a charge in a second charge storage layer.