Selectable Voltage Supply Circuit for Parasitic Current Inhibition

The patent introduces NMOS transistors as intermediary devices between the voltage supplies and the load. These NMOS transistors act as mediators that can selectively connect different voltage supplies without the parasitic diode conduction issues inherent in PMOS-based switching. The NMOS transistors are controlled by selection signals to enable precise voltage supply selection while eliminating the harmful parasitic current paths that would otherwise cause latch-up conditions.

The patent changes the key parameter of the switching transistor from PMOS to NMOS type. This parameter change fundamentally alters the electrical characteristics of the switching element, eliminating the parasitic diode conduction problem that occurs in PMOS transistors when subjected to large voltage differences. The NMOS transistors provide the same voltage selection functionality without the harmful side effects, as they do not exhibit the same parasitic diode behavior under these conditions.

The NMOS transistors serve as intermediary switching elements that safely handle large voltage differences between supplies. Unlike PMOS transistors whose parasitic diodes would conduct and cause breakdown under large voltage differences, the NMOS transistors provide a reliable switching mechanism that can tolerate and manage large voltage variations without compromising device reliability.

The patent effectively converts the potential harm of large voltage differences into a benefit by using NMOS transistors that are inherently more tolerant of voltage variations. The large voltage differences that would normally cause parasitic diode conduction and breakdown in PMOS devices are instead utilized to provide robust voltage selection capability with the NMOS implementation, turning a reliability risk into an enhanced operational range.

The patent introduces control circuitry as an intermediary between the selection signals and the NMOS switching transistors. This control circuitry precisely manages the timing of transistor activation and deactivation, ensuring that substrate currents are properly managed during transitions. The intermediary control mechanism coordinates the switching actions to prevent the timing-related substrate current issues that plague conventional switch implementations.

The NMOS-based switching circuitry with its integrated control logic essentially manages its own timing and substrate current issues through self-service mechanisms. The circuit is designed to automatically handle the coordination of multiple switching events, ensuring that substrate currents are contained and that latch-up conditions are prevented without requiring external timing control or complex external circuitry.