Semiconductor Selection Structure Layout for Programmable Signal Paths
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Solution Overview
Problem
Challenges arise during the scaling-down process of semiconductor devices, affecting quality, yield, performance, and reliability, and increasing complexity.
Innovation Solution
A semiconductor device design featuring selection structures and vias that allow for multiple signal paths to be formed based on user programming, optimizing semiconductor real estate and enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor device dimensions are scaled down to increase computing ability, then device density and computing power are improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The selection structure is divided into multiple discrete components including top selection structures, bottom selection structures, and intermediate selection structures. Each structure can be independently formed and controlled, allowing complex functionality to be built from simpler modular elements that are easier to manufacture at scaled dimensions
Solution Approach 2:
The patent introduces vertical stacking of selection structures at different levels (top, intermediate, bottom) to create three-dimensional signal routing paths. This adds a vertical dimension to the traditionally planar semiconductor layout, increasing functional density without requiring proportional increases in lateral manufacturing precision
2Adaptability or versatility
If more functional elements are integrated into the semiconductor device, then device capability is improved, but the area occupied and manufacturing complexity increase
Solution Approach 1:
Multiple selection structures are nested vertically within each other at different levels, with top selection structures positioned above intermediate structures which are positioned above bottom structures. This nesting arrangement allows multiple functional elements to occupy overlapping horizontal footprints at different vertical levels, maximizing the use of semiconductor real estate
Solution Approach 2:
The patent utilizes vertical stacking to place multiple selection structures at different heights (first vertical level, second vertical level, third vertical level), enabling more functional elements to be integrated within the same horizontal area by exploiting the third dimension
3Speed
If selection structures are positioned closer to the main signal pad, then connection efficiency is improved, but interference and crosstalk increase
Solution Approach 1:
Selection structures are positioned at different vertical levels relative to the main signal pad (some at the same vertical level, others at lower vertical levels). This vertical separation allows structures to be spatially closer for efficient connection while maintaining sufficient horizontal spacing to reduce interference and crosstalk
Data Source
AI summary
A semiconductor device includes a first top selection structure and a second top selection structure at a same vertical level as and separated from a main signal pad, and respectively extending along different directions; a first ground layer at the same vertical level as and separated from the main signal pad and the top selection structures; a first bottom selection structure at a vertical level lower than the main signal pad and partially overlapped with the top selection structures and the first ground layer in a top-view perspective; a first top via between the first ground layer and the first bottom selection structure; second top vias between the top selection structures and the first bottom selection structure; first insulating layers between the second top vias and the first bottom selection structure; and a wiring pad on the main signal pad and the top selection structures.