Flash Memory Controller Decoder with Selective Codeword Writing
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Solution Overview
Problem
Traditional flash memory systems face challenges in meeting system-level memory bandwidth requirements due to process yield limitations, leading to high power consumption during simultaneous reading and writing in high-noise environments, particularly in iterative decoding calculations.
Innovation Solution
A decoder circuit and flash memory controller are designed with a variable node circuit, variable-to-check circuit, check node circuit, check-to-variable circuit, and syndrome calculation circuit to reduce reading and writing frequency by selectively storing and writing hard decision results based on difference values, using a memory circuit to minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all small physical memories operate at the same time to meet system-level bandwidth requirements, then memory bandwidth is improved, but power consumption increases due to simultaneous reading and writing in high-noise environments
Solution Approach 1:
The patent applies partial action by selectively operating only the necessary number of memory units based on the actual data processing requirements. Instead of all memory units operating simultaneously, the system activates only the minimum required units to meet bandwidth demands, thereby reducing overall power consumption while maintaining necessary productivity levels.
Solution Approach 2:
The system dynamically adjusts the number of active memory units based on real-time bandwidth requirements and noise conditions. The memory controller monitors system demands and activates or deactivates memory units accordingly, transforming the static all-or-nothing operation into a dynamic, adaptive system that optimizes the balance between bandwidth and power consumption.
2Reliability
If iterative decoding calculation is performed in high-noise environment, then error correction capability is improved, but power consumption increases due to frequent reading and writing operations
Solution Approach 1:
The patent implements preliminary action by performing soft decoding calculations using previously read data before initiating new read operations. The system utilizes the existing data in memory to perform iterative decoding computations, and only performs additional reading when absolutely necessary, thereby reducing the frequency of power-consuming read/write operations while maintaining error correction capability.
Solution Approach 2:
The system maintains continuous useful action by keeping data in memory for repeated decoding iterations rather than repeatedly reading from and writing to memory. The iterative decoding process continuously operates on the stored data, maximizing the utilization of already-accessed data and minimizing additional I/O operations that consume power.
3Quantity of substance
If memory depth is increased to meet bandwidth requirements, then memory capacity is improved, but manufacturing precision becomes more difficult due to process yield limitations
Solution Approach 1:
The patent applies segmentation by dividing the memory system into multiple smaller, independent memory units or banks. Instead of relying on a single large-depth memory that is difficult to manufacture with high yield, the system uses several smaller memory units that can be manufactured more reliably. These segmented units work together to provide the required total capacity and bandwidth.
Solution Approach 2:
The system merges multiple smaller memory units to achieve the required total memory capacity and bandwidth. By combining several manageable memory blocks, each with feasible manufacturing specifications, the system attains the aggregate performance of larger memory systems while avoiding the process yield issues associated with manufacturing single large-depth memory structures.
Data Source
AI summary
A decoding method includes: generating or updating a variable-to-check message and generating a log-likely ratio according to a channel value; generating a converted variable-to-check message according to the variable-to-check message; generating a check-to-variable message according to the converted variable-to-check message; generating a converted check-to-variable message according to the check-to-variable message to update the variable-to-check message and the log-likely ratio; performing a hard decision according to the log-likely ratio to determine whether to flip bit(s) of a specific codeword to generate an output codeword; and comparing a reference value with a hard decision result to generate a difference value and selectively writing the hard decision result into the memory circuit according to the difference value to decrease the number of performing writing operation of the memory circuit.