Selective Copyback Mechanism for Memory Sub-Systems

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Solution Overview

Problem

Existing memory sub-systems face performance penalties due to the need for extensive scanning and error checking of SLC data before performing copyback operations into HLC memory, leading to increased latency and data bus congestion.

Innovation Solution

Implementing a selective copyback mechanism where the memory sub-system controller performs data validity and integrity checks to determine whether a blind or corrective copyback operation is necessary, optimizing the copyback process based on the access rate and error rate of the data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If extensive scanning and error checking is performed on SLC data before copyback operations, then data integrity is improved, but latency increases and data bus congestion occurs

Engineering Contradiction:
Improvedata integrityVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary classification of SLC data into frequent-access and infrequent-access categories before copyback operations. This preliminary action allows the system to apply different error checking strategies in advance, ensuring data integrity for infrequent-access data while avoiding unnecessary checking for frequent-access data, thereby reducing latency and data bus congestion

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system applies different error checking intensities to different portions of SLC data based on access patterns. Infrequent-access data receives extensive scanning and error checking to ensure integrity, while frequent-access data undergoes minimal or no error checking. This local differentiation resolves the contradiction by tailoring the reliability measure to the specific needs of each data portion

Inventive Principle:
Principle #3Local quality

2Reliability

If extensive scanning and error checking is performed on SLC data before copyback operations, then data integrity is improved, but data bus congestion increases

Engineering Contradiction:
Improvedata integrityVSAvoiddata bus efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary classification of SLC data into frequent-access and infrequent-access categories before copyback operations. This preliminary action allows the system to apply different error checking strategies in advance, ensuring data integrity for infrequent-access data while avoiding unnecessary checking for frequent-access data, thereby reducing latency and data bus congestion

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system applies different error checking intensities to different portions of SLC data based on access patterns. Infrequent-access data receives extensive scanning and error checking to ensure integrity, while frequent-access data undergoes minimal or no error checking. This local differentiation resolves the contradiction by tailoring the reliability measure to the specific needs of each data portion

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12272412B2Performing selective copyback in memory devices
Publication Date: 2025.04.08 MICRON TECHNOLOGY INC
  • US12272412B2 patent drawing
  • US12272412B2 patent drawing
  • US12272412B2 patent drawing

AI summary

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a set of memory cells of the memory device; responsive to determining that the data validity metric value satisfies a first threshold criterion, performing a data integrity check on the set of memory cells to obtain a data integrity metric value; and responsive to determining that the data integrity metric value satisfies a second threshold criterion, performing an error handling operation on the data stored on the set of memory cells to generate corrected data.