Selective Epitaxial MOSFET Layout for SOI and Bulk Silicon
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Solution Overview
Problem
The formation of epitaxial layers in both SOI and bulk silicon regions of semiconductor devices is hindered by etching residues from gate insulating films, leading to non-uniform epitaxial growth and variations in electrical characteristics, particularly when the gate insulating film in the bulk silicon region is thicker, affecting the reliability and performance of MOSFETs.
Innovation Solution
The solution involves forming epitaxial layers only in the source and drain regions of MOSFETs in the SOI region, while omitting epitaxial layers in the bulk silicon region to prevent etching residue interference, ensuring uniform growth and improved electrical characteristics by using different gate oxide film thicknesses for each region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If epitaxial layers are formed in both SOI and bulk silicon regions, then integration density and operation speed are improved, but etching residues from thicker gate insulating films in bulk silicon region cause non-uniform epitaxial growth and electrical characteristic variations
Solution Approach 1:
The substrate is divided into two distinct regions: SOI region with thinner gate insulating film where epitaxial layers are formed, and bulk silicon region with thicker gate insulating film where epitaxial layers are omitted. This segmentation allows each region to be optimized independently, preventing etching residues in the bulk silicon region from contaminating the epitaxial growth process while maintaining high integration density through selective epitaxial formation in the SOI region.
Solution Approach 2:
Different structural configurations are applied to different regions of the substrate. The SOI region receives full epitaxial layer formation for high-speed operation, while the bulk silicon region intentionally omits epitaxial layers to avoid etching residue contamination. This local quality differentiation ensures that each region's specific characteristics are optimized for its intended function without compromising overall device performance.
2Reliability
If gate insulating film thickness is increased in bulk silicon region for higher breakdown voltage, then device reliability is improved, but etching residues remain during gate insulating film processing, preventing desirable epitaxial layer formation
Solution Approach 1:
The epitaxial layer formation process is selectively extracted or omitted from the bulk silicon region where thicker gate insulating films are present. By removing the epitaxial formation step specifically from regions with thicker gate insulating films, the patent avoids the problem of etching residues contaminating the epitaxial growth, while still allowing high breakdown voltage devices to be formed in the bulk silicon region with their inherently higher voltage tolerance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance and reliability of semiconductor devices by preventing epitaxial layer formation in the bulk silicon region with thicker gate oxide films, reducing variations and maintaining high electrical performance.
Implementation Method 1
etching residues from the processing of the gate insulating film
Implementation Method 2
an epitaxial layer is formed in source and drain regions of the MOSFET in the SOI region
Data Source
AI summary
On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.