Selective Erasure in Stacked NAND Flash Memory via Sub-Block Control
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Solution Overview
Problem
The existing stacked NAND-type flash memory devices face challenges in reducing the size of the minimum unit for data erasure, which increases the circuit area and decreases data storage capacity, necessitating the development of a technology that allows selective erasure of only a part of the memory cells in one memory block.
Innovation Solution
A nonvolatile semiconductor memory device with a memory cell array comprising stacked memory strings and select transistors, where the control circuit applies specific voltages to word lines and select transistors to selectively erase data by maintaining non-selected memory transistors in a non-conductive state, preventing erasure of untargeted memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple memory strings are connected in common to one word line to decrease circuit area, then the circuit area of peripheral circuits is reduced, but the size of the minimum unit for data erasure increases
Solution Approach 1:
The patent introduces a sub-block division within each memory block, where each sub-block contains a specific number of memory units (e.g., 32 memory units). This segmentation allows the erasure operation to be performed at the sub-block level rather than the entire block level, effectively dividing the large memory block into smaller manageable units for selective erasure.
Solution Approach 2:
The patent applies different voltage conditions to different regions within the same memory block. By controlling the word line voltages locally (applying verification voltage to specific word lines while maintaining other word lines at different potentials), the erasure operation can be selectively applied to specific memory units within a block, enabling fine-grained control over which data is erased.
2Quantity of substance
If the stacking number increases to improve bit density, then the data storage capacity increases, but the size of one memory block increases causing the minimum unit for data erasure to be larger
Solution Approach 1:
The patent divides each memory block into multiple sub-blocks, where each sub-block contains a fixed number of memory units (e.g., 32 memory units). This segmentation allows the system to maintain large storage capacity through stacking while enabling erasure operations at the smaller sub-block level, effectively decoupling the total capacity from the erasure unit size.
Solution Approach 2:
The patent introduces a new hierarchical dimension for memory organization by creating sub-blocks within blocks. This additional level of organization allows selective erasure to operate in a finer granularity dimension, independent of the overall block size determined by stacking height, thus enabling small erasure units even in high-capacity stacked devices.
3Quantity of substance
If selective erasure of a part of memory cells is implemented, then the data storage capacity is enhanced, but the control complexity increases
Solution Approach 1:
The patent segments the memory block into sub-blocks and introduces verification word lines that can be independently controlled. This segmentation provides a structured framework for selective erasure, where the control circuit only needs to manage voltage application at the sub-block level rather than individually addressing each memory cell, thus limiting the increase in control complexity.
Solution Approach 2:
The verification word lines serve multiple functions: they act as control lines for selective erasure, as verification lines for data validation, and as part of the normal word line structure. This multi-functionality reduces the need for entirely separate control mechanisms, thereby limiting the increase in control circuit complexity while enabling selective erasure capability.
Data Source
AI summary
A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation.