Selective High-k Gate Dielectric Deposition for Lower Parasitic Capacitance
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Solution Overview
Problem
The deposition of high-κ gate dielectric material on gate spacers or inner spacers in GAA FETs increases parasitic capacitance, reducing the effective gate length and worsening leakage currents.
Innovation Solution
A method is developed to selectively deposit high-κ dielectric material on an interfacial layer formed on the channel surface between source and drain, using a metal-containing precursor, purge gas, and alcohol, while avoiding deposition on low-κ dielectric surfaces, followed by annealing and dipole layer removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-κ dielectric material is deposited on gate spacers or inner spacers, then the gate dielectric coverage is improved, but the effective gate length is reduced and parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by creating different surface properties in different regions of the substrate. The gate spacer and inner spacer surfaces are treated to be non-reactive toward the high-κ dielectric precursor, while the channel surface remains reactive. This is achieved through selective surface preparation steps that modify the chemical properties of specific regions, allowing the deposition process to naturally select where to deposit material based on local surface characteristics rather than applying a uniform treatment across the entire substrate.
Solution Approach 2:
The patent introduces an intermediary layer or surface treatment that mediates between the deposition process and the underlying structures. This intermediary mechanism (such as a self-assembled monolayer or surface-terminated layer) prevents direct reaction between the high-κ dielectric precursor and the gate spacer/inner spacer surfaces, while allowing the desired deposition to occur on the channel surface. The intermediary acts as a selective barrier that controls material deposition based on spatial location.
2Object-affected harmful factors
If high-κ dielectric material is selectively deposited only on the channel, then parasitic capacitance is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The patent employs self-service by designing a deposition process that uses the structures themselves to guide the deposition pattern. The gate spacer and inner spacer surfaces inherently possess properties (through prior processing steps) that cause them to reject the high-κ dielectric material, while the channel surface naturally accepts it. The system uses its own built-in surface characteristics to control the deposition, eliminating the need for external masking or complex patterning steps that would otherwise be required to achieve selective deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the effective gate length and reduces parasitic capacitance, improving the performance of GAA FETs by selectively depositing high-κ dielectric material without affecting the gate spacer or inner spacer.
Implementation Method 1
selectively depositing a high-κ dielectric layer directly on the interfacial layer relative to the low-κ dielectric layer by exposing the semiconductor substrate to a metal-containing precursor
Implementation Method 2
exposing the semiconductor substrate to a metal-containing precursor, a purge gas, an alcohol, and the purge gas
Implementation Method 3
annealing the semiconductor substrate at a temperature of less than or equal to 1000° C. to drive in metallic atoms from the dipole layer and densify the high-κ dielectric layer
Implementation Method 4
annealing the semiconductor substrate at a temperature of less than or equal to 1000° C. to drive in metallic atoms from the dipole layer and densify the high-κ dielectric layer
Data Source
AI summary
A processing method includes forming an interfacial layer on a surface of a channel comprising silicon (Si) located between a source and a drain on a semiconductor substrate including a low-κ dielectric layer, and selectively depositing a high-κ dielectric layer directly on the interfacial layer relative to the low-κ dielectric layer by exposing the semiconductor substrate to a metal-containing precursor, a purge gas, an alcohol, and the purge gas.