Selective Memory Programming with Verify-Loop Bitline Adjustment

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Solution Overview

Problem

Memory systems face challenges in maintaining consistent charge retention due to varying charge loss rates among memory cells, leading to unpredictable threshold voltage distributions and increased bit error rates, particularly as the systems age, which affects read window budget and overall reliability.

Innovation Solution

Implementing a selective slow programming convergence (SSPC) operation with program verify loop dependent adjustment of bitline voltage to optimize read window budget (RWB) by adjusting bitline voltage levels based on the program verify loop count, ensuring faster cells experience more charge loss and slower cells less, resulting in tighter threshold voltage distributions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional programming operations are used, then programming speed is maintained, but threshold voltage distributions become unpredictable and bit error rates increase

Engineering Contradiction:

Improvebit error rateVSAvoidprogramming speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent segments the memory cell population into multiple groups based on their programming speeds. Fast cells, slow cells, and medium cells are identified and handled differently through selective programming operations. This segmentation allows the system to maintain reliability by addressing the specific characteristics of each cell group while preserving overall programming efficiency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different programming convergence criteria and bitline voltage adjustments to different local groups of cells based on their individual programming characteristics. Each cell group receives tailored programming parameters, enabling the system to optimize reliability for each local region without compromising the performance of other regions.

Inventive Principle:

Principle #3Local quality

2Manufacturing precision

If bitline voltage is adjusted dynamically during program verify loops, then threshold voltage distributions tighten, but device complexity increases

Engineering Contradiction:

Improvethreshold voltage distributionVSAvoidprogramming operation complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent implements dynamic bitline voltage adjustment during the program verify loops based on the detected programming speed of each cell group. The bitline voltage is not fixed but adapts in real-time during programming operations, allowing the system to achieve tighter threshold voltage distributions while managing complexity through automated detection and adjustment mechanisms.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent employs feedback mechanisms where the program verify loops detect the actual programming speed of cells and use this information to adjust subsequent programming parameters. This feedback-driven approach enables automatic optimization of threshold voltage distributions without requiring manual intervention or overly complex predetermined control logic.

Inventive Principle:

Principle #23Feedback

3Reliability

If selective slow programming convergence is applied to all cells, then read window budget improves, but programming time increases

Engineering Contradiction:

Improveread window budgetVSAvoidprogramming time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent segments cells into fast, slow, and medium programming speed groups and applies selective slow programming convergence only to the necessary groups. This segmentation ensures that read window budget is improved for cells that require it while avoiding unnecessary time penalties for cells that can be programmed quickly without additional convergence operations.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different programming convergence strategies to different local cell groups based on their individual characteristics. Fast cells receive standard programming operations, while slow and medium cells receive enhanced convergence operations with adjusted bitline voltages. This localized approach optimizes read window budget where needed without unnecessarily extending programming time for all cells.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250226039A1Selective slow programming convergence program operation with program verify loop dependent bitline voltage adjustment

Publication Date: 2025.07.10 MICRON TECHNOLOGY INC

AI summary

Processing logic in a memory sub-system receives a request to execute a programming operation to program cells of a memory device to a set of programming levels. The processing logic executes a first program verify loop associated with a programming level of the set of programming levels, where the first program verify loop comprises applying an initial bitline voltage to a subset of the cells having a threshold voltage in a range between a pre-program verify voltage and a program verify voltage. The processing logic executes a subsequent program verify loop associated with the programming level, wherein the subsequent program verify loop comprises applying an adjusted bitline voltage to the subset of the cells.