Selective Metal Cap Formation for Low-Resistance FinFET Gates
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area with reduced minimum feature sizes, challenges arise in the fabrication process that affect device performance and efficiency, particularly in forming multi-gate transistors like FinFETs and GAA devices.
Innovation Solution
A method is developed for fabricating multi-gate devices, including the formation of a continuous metal cap over a metal gate structure to reduce gate resistance, which involves forming a high-K/metal gate stack and using a metal cap to connect via gate conductors, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an anti-reaction layer is formed over the metal gate structure to prevent oxidation, then oxidation protection is improved, but metal cap deposition is hindered
Solution Approach 1:
The patent removes the anti-reaction layer in specific regions to enable metal cap deposition. The etch hole formation process extracts the anti-reaction layer material where the metal cap needs to be deposited, allowing the metal cap to directly contact the metal gate structure in those regions while maintaining oxidation protection in other areas.
Solution Approach 2:
The patent creates different local properties by selectively removing the anti-reaction layer in etch holes while maintaining it in other areas. This allows the metal cap to be deposited in specific locations where needed for electrical connection, while the anti-reaction layer remains in place elsewhere to provide oxidation protection.
2Ease of operation
If the metal gate structure is exposed for via gate conductor connection, then electrical connection is improved, but gate resistance increases
Solution Approach 1:
The patent introduces a metal cap as an intermediary layer between the via gate conductor and the metal gate structure. This metal cap provides a low-resistance electrical connection path while enabling proper via formation and connection to the metal gate structure.
3Reliability
If continuous metal cap is formed over metal gate structure, then gate resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the metal cap in a specific sequence: first creating etch holes through the anti-reaction layer, then depositing metal cap material to fill these holes and form a continuous cap over the metal gate structure. This preliminary formation of the continuous metal cap simplifies subsequent via gate conductor connection processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces gate resistance and enhances device performance by allowing for effective connection of via gate conductors without interference from anti-reaction layers, facilitating gate height scaling and overall device efficiency.
Implementation Method 1
depositing a first metal material comprising tungsten (W) material or molybdenum (Mo) material over the gate structure which forms a discontinuous metal cap using first atomic layer deposition (ALD) operations; depositing second metal material comprising W or Mo over the gate structure to create a continuous metal cap using second ALD operations
Implementation Method 2
selectively removing the anti-reaction layer using dilute hydrofluoric acid (HF)
Implementation Method 3
containing growth of the metal cap by removing unwanted metal material from side spacers via wet etching operations using an ozone solution
Data Source
AI summary
Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a high-k dielectric layer, a p-type work function layer, an n-type work function layer, a dielectric anti-reaction layer, and a glue layer; and a continuous metal cap over the gate structure formed by metal material being deposited over the gate structure, a portion of the anti-reaction layer being selectively removed, and additional metal material being deposited over the gate structure. A semiconductor fabrication method includes: receiving a gate structure; flattening the top layer of the gate structure; precleaning and pretreating the surface of the gate structure; depositing metal material over the gate structure to form a discontinuous metal cap; selectively removing a portion of the anti-reaction layer; depositing additional metal material over the gate structure to create a continuous metal cap; and containing growth of the metal cap.