Selective Sub-Resolution Assist Feature Positioning for Interconnect Optimization
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Solution Overview
Problem
Conventional photolithography techniques face limitations in patterning small features due to light wavelength constraints, leading to iso-dense bias and increased parasitic capacitance, which affects circuit performance, especially in sub-100 nm technologies.
Innovation Solution
A method for selectively positioning sub-resolution assist features (SRAFs) in photomasks to optimize interconnect patterns based on circuit performance metrics, such as RC delay and crosstalk, by determining whether SRAFs improve performance compared to patterns without SRAFs, and positioning them accordingly to reduce parasitic capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If SRAFs are added to correct iso-dense bias, then manufacturing precision of isolated features is improved, but device complexity increases
Solution Approach 1:
The patent applies different treatments to different regions of the mask pattern: isolated features receive SRAFs while dense features do not. This local differentiation allows precision correction where needed without unnecessarily complicating the entire mask pattern.
Solution Approach 2:
The patent dynamically adjusts the mask pattern by selectively adding or removing SRAFs based on the specific geometric context of each feature. The decision to add SRAFs is not static but depends on real-time analysis of feature isolation, spacing, and density requirements.
2Manufacturing precision
If interconnect width is increased to overcome photolithographic limitations, then manufacturing precision is improved, but parasitic capacitance increases
Solution Approach 1:
The patent changes the optical parameters of the photolithography process by introducing SRAFs that modify light distribution. This allows achieving the desired interconnect width without increasing the physical width, thereby maintaining electrical performance while achieving dimensional precision.
Solution Approach 2:
SRAFs act as intermediary elements that mediate between the light source and the photoresist. They modify the optical field to achieve precise patterning without requiring larger physical features, thus preventing the generation of harmful parasitic capacitance.
3Ease of manufacture
If all interconnect patterns receive the same processing, then ease of manufacture is improved, but circuit performance deteriorates
Solution Approach 1:
The patent implements local quality by applying different processing treatments to different interconnect patterns based on their specific requirements. Short interconnects receive one treatment while long interconnects receive another, optimizing performance for each case rather than using a uniform approach.
Solution Approach 2:
The manufacturing process becomes dynamic and adaptive, automatically selecting different processing parameters based on interconnect characteristics such as length and routing. This allows the system to maintain ease of manufacture through automation while achieving optimized performance for each specific interconnect.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved circuit performance by selectively applying narrower or wider interconnect widths based on route length, reducing overall parasitics and enhancing circuit efficiency.
Implementation Method 1
The SRAFs are designed to increase the light intensity of an isolated feature region so that it is more similar to denser feature regions
Data Source
AI summary
The present application is directed to a method of selectively positioning sub-resolution assist features (SRAF) in a photomask pattern for an interconnect. The method comprises determining if a first interconnect pattern option will result in improved circuit performance compared with a second interconnect pattern option, where the first option is designed to be formed with SRAF and the second option is designed to be formed without SRAF. If it is determined that the first option will result in improved circuit performance, the first pattern option is selected as a target pattern and one or more SRAF patterns are positioned to facilitate patterning of the first pattern option. If it is not determined that the first option will result in improved performance, the second pattern option is selected as a target pattern.