Selective Work Function Gate Structures for Ultra-Low Threshold GAA FETs
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down metal oxide semiconductor field effect transistors (MOSFETs) to achieve ultra-low threshold voltages while maintaining manufacturing complexity and cost-effectiveness, particularly in forming gate structures with nanostructured channel regions.
Innovation Solution
The development of gate structures for finFETs and gate-all-around (GAA) FETs with Al-based n-type work function metal layers and Al-free p-type work function metal bi-layers, along with selective formation of Si capping layers, to achieve ultra-low threshold voltages and reduce gate stack thickness by 50% to 75% compared to conventional methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional gate structures are used to scale down MOSFETs, then device dimensions are reduced, but manufacturing complexity increases
Solution Approach 1:
The gate structure is segmented into multiple functional layers: gate dielectric layer, first work function metal layer (Al-based for n-type), second work function metal layer (Al-free for p-type), and selective Si capping layers. This segmentation allows independent optimization of each layer's properties to achieve ultra-low threshold voltages while simplifying the overall manufacturing process through standardized layer formation sequences
Solution Approach 2:
Different work function metal layers are applied locally to different device regions: Al-based metal layers are formed in n-type FET regions to achieve low threshold voltages, while Al-free metal layers are formed in p-type FET regions. This local differentiation enables tailored electrical characteristics for each transistor type within the same integrated circuit, reducing the need for separate processing lines
2Manufacturing precision
If gate stack thickness is reduced to achieve ultra-low threshold voltages, then threshold voltage control improves, but gate structure reliability may deteriorate
Solution Approach 1:
The gate structure employs composite material stacks combining gate dielectric materials (e.g., HfO2, SiO2), Al-based work function metals for n-type devices, Al-free work function metals for p-type devices, and selective Si capping layers. This composite approach allows the thin gate stack to maintain mechanical integrity and electrical reliability while achieving ultra-low threshold voltages through optimized material combinations rather than simply reducing thickness
Solution Approach 2:
Si capping layers are selectively formed on top of work function metal layers before subsequent processing steps. These capping layers serve as protective cushions that prevent oxidation and degradation of the work function metals during manufacturing and device operation, thereby maintaining gate structure reliability even when the overall gate stack thickness is reduced to achieve ultra-low threshold voltages
3Manufacturing precision
If separate gate structures are formed for n-type and p-type FETs, then threshold voltage optimization improves, but manufacturing efficiency decreases
Solution Approach 1:
The gate structure methodology is designed as a universal process that simultaneously forms both n-type and p-type FET gate structures in the same integrated circuit. By using Al-based work function metal layers for n-type devices and Al-free work function metal layers for p-type devices within the same gate stack architecture, the process achieves differentiated threshold voltage optimization for both transistor types through a single unified manufacturing flow, eliminating the need for separate processing lines and significantly improving manufacturing efficiency
Data Source
AI summary
The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.