Selector Layer Formation in Semiconductor Memory to Prevent Etch Damage

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional methods for forming doped selector layers in semiconductor devices lead to increased device height and etch damage during patterning, compromising hard mask margins.

Innovation Solution

The formation of blanket-doped selector layers by introducing oxygen and/or nitrogen into electrode contacts and dielectric layers through ion implantation, eliminating the need for a separate dielectric layer, thereby maintaining hard mask margins and preventing etch damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional methods for forming doped selector layers are used, then the selector layer can be formed, but the device height increases and etch damage occurs during patterning

Engineering Contradiction:
Improvepatterning precisionVSAvoiddevice height
Core Design Contradiction:
Manufacturing precisionVSLength of stationary object

Solution Approach 1:

The patent merges the dielectric layer and electrode contact into a single integrated structure. The electrode contact extends through the dielectric layer to directly contact the lower conductive line, eliminating the need for a separate dielectric layer and reducing overall device height while maintaining hard mask margins during patterning.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The electrode contact is configured to extend in the vertical dimension through the dielectric layer, changing the spatial arrangement from separate horizontal layers to a vertical penetration structure. This dimensional change reduces the horizontal footprint and maintains patterning margins while achieving the necessary electrical connection.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If conventional methods for forming doped selector layers are used, then the selector layer can be formed, but etch damage occurs during patterning

Engineering Contradiction:
Improvepatterning precisionVSAvoidetch damage
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The integration of the dielectric layer and electrode contact creates a unified structure that maintains consistent hard mask margins during patterning. This merged structure eliminates the interface between separate layers that would otherwise be vulnerable to etch damage, allowing for more precise and damage-free patterning of the doped selector layer.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If a separate dielectric layer is used, then electrical insulation is provided, but the device height increases

Engineering Contradiction:
Improveelectrical insulationVSAvoiddevice height
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent combines the dielectric layer and electrode contact into a single integrated component. The electrode contact extends through the dielectric material, which provides electrical insulation between the upper and lower conductive lines, while the integrated structure reduces the overall device height compared to using separate layers.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The integrated dielectric layer and electrode contact structure serves multiple functions simultaneously: it provides electrical insulation between conductive lines, establishes electrical connection through the contact portion, and reduces device height. This multi-functional design eliminates the need for separate dedicated dielectric and contact layers.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method maintains hard mask margins and prevents etch damage, ensuring precise patterning and reducing overall device height in semiconductor devices.

Implementation Method 1

performing a first ion implantation process to form a first sub dielectric layer within the contact and a second sub dielectric layer within the first dielectric layer by converting a portion of the contact into the first sub dielectric layer and a portion of the first dielectric layer into the second sub dielectric layer

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS12507418B2Semiconductor device and method for fabricating the same
Publication Date: 2025.12.23 SK HYNIX INC
  • US12507418B2 patent drawing
  • US12507418B2 patent drawing
  • US12507418B2 patent drawing

AI summary

A semiconductor device may include: a first conductive line; a second conductive line disposed over the first conductive line to be spaced apart from the first conductive line; a variable resistance layer disposed over the first conductive line and below the second conductive line; at least one of a first dielectric layer or a second dielectric layer; at least one of a first contact or a second contact; and at least one of a first doped selector layer or a second doped selector layer.