Self-Addressing DRAM With In-Memory Sorting for Variable-Length Data
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Solution Overview
Problem
Existing memory technologies face inefficiencies in managing variable length records and strings, which do not map cleanly to fixed-sized rows, leading to wasted memory and computational overhead, while traditional sorting algorithms consume significant computing resources and pipeline processing is limited by memory transistors optimized for storage rather than switching.
Innovation Solution
The introduction of Self-Addressing Dynamic Random Access Memory (SADRAM) with a logic layer that includes a sequencer to manage DRAM rows in sorted order, perform symbolic addressing, and implement mitosis to handle overflow, while using a SamPU for control and a logic layer closely bound to the memory array to perform computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional memory technologies are used to store variable length records, then memory capacity is sufficient, but memory usage is inefficient and computational overhead increases
Solution Approach 1:
The memory system performs sorting and indexing operations autonomously through hardware sequencers that automatically place records in sorted order during write operations, eliminating the need for CPU-intensive sorting algorithms and reducing computational overhead while maintaining efficient memory usage
Solution Approach 2:
The patent replaces software-based sorting algorithms with hardware sequencers that perform sorting operations at the memory level through parallel comparison and swapping mechanisms, substituting complex computational processes with dedicated hardware that operates independently of the CPU
2Ease of operation
If traditional sorting algorithms are used to organize data, then data can be sorted, but computing resources are consumed significantly
Solution Approach 1:
The sorting function is segmented into parallel hardware sequencers that operate independently on different portions of the data simultaneously, allowing multiple sorting operations to proceed in parallel and reducing total computing time and resource consumption
Solution Approach 2:
The hardware sequencers perform sorting operations in advance during the data write process, so that data is already organized before it is needed for processing, eliminating the need for separate sorting steps and reducing overall computing resource requirements
3Quantity of substance
If memory transistors are optimized for storage, then storage capacity is maximized, but pipeline processing efficiency is limited
Solution Approach 1:
The patent merges storage functionality with processing functionality by integrating hardware sequencers directly into the memory architecture, allowing the same physical infrastructure to both store data and perform sorting operations, thereby improving pipeline processing speed without sacrificing storage capacity
Solution Approach 2:
The memory system is designed to perform multiple functions - storage, sorting, and indexing - through the same hardware architecture, where memory transistors serve both as storage elements and as part of the processing pipeline, eliminating the need for separate processing hardware and improving overall system speed
Data Source
AI summary
Self-Addressing Dynamic Random Access Memory (SADRAM) includes Dynamic Random Access Memory (DRAM) and a logic layer having direct access to the DRAM which provides symbolic addressing services. These services are provided by sequencers realized in the logic layer. The sequencers maintains a DRAM row or row-pair in sorted order, finds a location within the row or row-pair for a new data element, and inserts the new data element into the row or row-pair—all while preserving the sorted order. The sequencer is a plurality sequencer groups, each sequencer group is a plurality of sequencer cells. The sequencer cells to perform a highly parallel pipeline insertion of a new data element. The logic layer also defines a Self-Addressing Memory Central Processing Unit (SamPU) which is operatively coupled to the sequencer and configured to control the sequencer. The logic layer also provides program memory for SamPU and a memory cache in which is built an index database. The database is managed by the SamPU and the sequencers. It is subject to mitosis to accommodate the overflow of any item in the index database.