Self-Align Contact Structure for Semiconductor Device Isolation
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Solution Overview
Problem
As semiconductor device dimensions decrease, the thickness of sidewall spacers becomes thinner, leading to potential short circuits between source/drain contacts and gate electrodes, necessitating improved electrical isolation techniques.
Innovation Solution
A self-align contact structure is implemented using a sacrificial layer with high etching selectivity, allowing for selective removal of gate and source/drain cap insulating layers to prevent short circuits and maintain process window integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sidewall spacer thickness is reduced to increase device density, then device density increases, but electrical isolation between source/drain contacts and gate electrodes deteriorates
Solution Approach 1:
A sacrificial layer is introduced as an intermediary element between the gate structure and source/drain contact regions. This sacrificial layer extends from the gate structure into the source/drain regions and is selectively removed to create contact holes, thereby mediating the electrical isolation requirement while enabling closer spacing of source/drain contacts relative to the gate structure.
Solution Approach 2:
The gate structure is segmented by introducing the sacrificial layer that extends laterally from the gate, creating distinct regions for contact formation. This segmentation allows the source/drain contacts to be positioned closer to the gate structure while maintaining electrical isolation through the selective removal process of the sacrificial layer.
2Reliability
If conventional sacrificial layer structure is used, then electrical isolation is improved, but manufacturing complexity increases due to additional patterning steps
Solution Approach 1:
The sacrificial layer formation is merged with the existing gate structure fabrication process. The sacrificial layer is formed using the same patterning steps as the gate structure, and its extension from the gate structure utilizes the existing sidewall spacer patterns, thereby combining multiple functions into a unified process flow that reduces overall manufacturing complexity.
Solution Approach 2:
The sacrificial layer serves multiple functions: it acts as a spacer during gate formation, provides electrical isolation during subsequent processing, and serves as a template for contact hole formation. This multi-functionality eliminates the need for separate dedicated structures for each function, reducing manufacturing complexity.
3Manufacturing precision
If self-align contact structure is implemented, then process window is improved, but etching selectivity requirements become more stringent
Solution Approach 1:
Different etching selectivities are applied to different regions of the sacrificial layer. The portion of the sacrificial layer extending from the gate structure into the source/drain regions requires high selectivity relative to the gate structure, while other portions may have different selectivity requirements. This local differentiation of quality requirements optimizes the self-align contact formation process window.
Solution Approach 2:
The etching process parameters are optimized to achieve the required selectivity for the self-align contact structure. By adjusting etching chemistry, temperature, and other parameters, the process window is maximized while meeting the stringent selectivity requirements for selective removal of the sacrificial layer from the gate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The self-align contact structure effectively prevents short circuits and reduces gate pattern density, enabling precise formation of conductive contact layers without compromising electrical isolation.
Implementation Method 1
The gate cap insulating layer is selectively removed from at least one of the gate structures, while at least one of remaining gate structures is protected, thereby exposing the gate electrode of the at least one of the gate structures. The source/drain cap insulating layer is selectively removed from at least one of the source/drain structures, while at least one of remaining source/drain structures is protected, thereby exposing the source/drain conductive layer of the at least one of the source/drain structures.
Data Source
AI summary
A semiconductor device includes a first gate structure, a second gate structure, a first source/drain structure and a second source/drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source/drain structure includes a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer. The second source/drain structure includes a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer.