Self-Aligned Backside Power Rail Contacts for Multi-Source Transistors
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Solution Overview
Problem
There is a need for semiconductor devices that can be connected to power rails using less cell area, as connecting semiconductors to power rails on the front of the cell requires significant cell area, and there is a trade-off between transistor size and speed, particularly in finFETs and hGAA structures.
Innovation Solution
A method involving forming an etch stop layer on a substrate, depositing an epitaxial layer, bonding a wafer device, grinding the substrate to reduce thickness, and forming contacts to the source/drain regions, allowing for self-aligned backside power rail connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power rail connections are made on the front of the cell, then electrical connectivity is achieved, but cell area is significantly consumed
Solution Approach 1:
The patent moves the power rail connections from the front surface (2D plane) to the backside of the substrate, utilizing the third dimension (depth/thickness) to resolve the area conflict. By forming contacts through the substrate thickness from the backside, the power rail connections no longer occupy front surface area, thereby reducing cell area consumption while maintaining electrical connectivity.
Solution Approach 2:
Instead of making power rail connections from the conventional front side, the patent inverts the approach by making connections from the backside of the substrate. This inversion allows the power rails to be formed independently on the backside, eliminating the need for front-side area and enabling separate optimization of front-side circuitry and back-side power distribution.
2Speed
If transistor gate width is increased to improve drive current and speed, then transistor performance is improved, but transistor size increases
Solution Approach 1:
The patent enables independent optimization of transistor dimensions by moving power connections to the backside. This allows the gate width to be increased for higher drive current and speed without proportionally increasing the front surface footprint, as the power rail area is now consumed on the backside rather than competing for front surface space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables efficient use of cell area by allowing power rail connections on the backside of the semiconductor device, reducing the need for front-side connections and optimizing transistor size and speed.
Implementation Method 1
selectively removing the etch stop layer
Implementation Method 2
bonding the wafer device to a bonding dummy wafer or Cu wafer with hybrid bonding
Implementation Method 3
grinding the substrate to form a substrate having a second thickness less than the first thickness
Implementation Method 4
forming an epitaxial layer on a top surface of the etch stop layer
Data Source
AI summary
A method of forming a semiconductor device is provided. The method includes forming a superlattice structure on a substrate and etching source and drain trenches adjacent to the superlattice structure. The source and drain trenches are expanded to form cavities, which are filled with a sacrificial material. A source region and a drain region are formed in the trenches. Contacts to the transistor and gate are formed. Backside processing is then performed by flipping the substrate, depositing an interlayer dielectric on the bottom surface, and etching a backside power rail via that is expanded into a damascene trench. The sacrificial material is removed to create openings extending to the damascene trench, and a metal fill is deposited in the openings and trench.