Self-Aligned Capping Layer for Interconnect Electromigration
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Solution Overview
Problem
The reliability of interconnect structures in electronic devices is compromised due to increased line edge roughness (LER) and reduced line-to-line spacing caused by isotropic growth of metal electromigration caps, leading to a higher risk of current shorting and device failure.
Innovation Solution
The method involves recessing conductive lines to form self-aligned channels in a dielectric layer, within which capping layers are selectively deposited to prevent electromigration, thereby controlling LER and maintaining line-to-line spacing, using a chemistry that ensures uniform etching independent of crystallographic orientation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal electromigration caps are grown using electroless plating, then electromigration protection is achieved, but line edge roughness increases and line-to-line spacing is reduced
Solution Approach 1:
A seed layer is deposited and patterned beforehand to define the precise location and boundaries where the electromigration cap will grow. This preliminary structure controls the lateral growth of the cap, preventing overhang formation and maintaining sharp line edges while still providing the necessary electromigration protection.
Solution Approach 2:
The seed layer acts as an intermediary between the substrate and the electromigration cap. It provides a controlled interface that directs the electroless plating growth, ensuring the cap forms only in desired locations with precise dimensional control, thereby reducing line edge roughness while maintaining protection functionality.
2Reliability
If metal electromigration caps are grown using electroless plating, then electromigration protection is achieved, but line-to-line spacing is reduced due to lateral growth
Solution Approach 1:
The seed layer is patterned with precise dimensions that account for the intended cap thickness. This preliminary structuring ensures that when the cap grows laterally during electroless plating, it does not encroach on adjacent lines, thereby maintaining adequate line-to-line spacing while still providing complete electromigration protection.
Solution Approach 2:
The dimensions of the seed layer are carefully controlled to compensate for the expected lateral growth of the cap. By adjusting the seed layer width parameter, the final cap dimensions are precisely controlled, ensuring adequate spacing between lines while maintaining sufficient cap thickness for electromigration protection.
3Reliability
If isotropic growth of metal caps occurs, then electromigration protection is provided, but overhang structures are formed that reduce spacing
Solution Approach 1:
The seed layer is formed with vertical sidewalls that act as growth boundaries. During electroless plating, the cap grows vertically from the seed layer but is laterally constrained by the seed layer's vertical walls, preventing overhang formation while maintaining the protective function against electromigration.
Solution Approach 2:
The growth geometry is made asymmetric by using a vertically-sided seed layer structure. This asymmetric configuration allows vertical growth for protection while preventing lateral overhang, creating a controlled growth pattern that eliminates the harmful overhang structures associated with isotropic growth on flat surfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of device failure and increases manufacturing yield by maintaining consistent line-to-line spacing and minimizing LER, ensuring reliable performance in nanoscale electronic devices.
Implementation Method 1
The electromigration caps, for example, caps 111-113, can be grown on the respective interconnect lines above a flat surface of the substrate using electroless plating
Implementation Method 2
The channels can be formed by etching the conductive lines to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation
Data Source
AI summary
At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.