Self-Aligned Cobalt Via Interconnects for Low Resistance BEOL
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Solution Overview
Problem
As semiconductor devices scale below 22 nm, via contact resistance increases due to the high resistance of PVD liner/barrier materials, and current lithography processes struggle to form self-aligned fine pitch vias, leading to performance limitations in BEOL interconnect structures.
Innovation Solution
The method involves forming a self-aligned cobalt via interconnect structure by selective CVD cobalt growth over a dielectric cap layer, eliminating the need for barrier and liner materials at the interface with the underlying wiring structure, and allowing lateral overgrowth to increase contact area with the upper wiring structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PVD liner/barrier deposition is used in dual-damascene fill processes, then the wiring structure is protected from diffusion, but the contact resistance increases due to higher resistance of liner/barrier materials
Solution Approach 1:
The patent removes the PVD liner/barrier materials from the via structure entirely. By using a self-aligned via approach where the via is formed directly through the dielectric cap layer without requiring separate liner/barrier deposition steps, the source of high contact resistance is eliminated while maintaining diffusion protection through the dielectric material itself
Solution Approach 2:
Instead of depositing liner/barrier materials to protect the via, the patent inverts the approach by using the dielectric cap layer as both the masking layer and the protective barrier. The via is formed by removing material rather than adding protective layers, fundamentally changing the sequence and method of protection
2Ease of manufacture
If conventional lithography processes are used, then the manufacturing process is simple, but self-aligned fine pitch vias cannot be formed at 14 nm and below
Solution Approach 1:
The patent employs a self-aligned via formation process where the dielectric cap layer serves as its own masking layer. The via automatically aligns with the underlying wiring structure because the cap layer is deposited conformally over the wiring, eliminating the need for separate photolithography alignment steps and enabling fine pitch vias at 14 nm and below
Solution Approach 2:
The dielectric cap layer is deposited in advance over the wiring structure before via formation. This preliminary deposition creates the self-aligned masking structure that guides subsequent via etching, ensuring precise alignment without requiring complex lithography processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces interfacial resistance, prevents electromigration, and enhances contact area, thereby improving semiconductor device performance by minimizing contact resistance and increasing the contact area between the via interconnect and the upper wiring structure.
Implementation Method 1
forming a self-aligned via interconnect structure in direct electrical contact with the metal material of the wiring structure by overfilling the opening with a metal or metal-alloy growth process
Implementation Method 2
electroplating a metal or metal-alloy material on the liner material to complete formation of an upper wiring structure
Data Source
AI summary
A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure.