Self-Aligned Contact Formation via Oxidizable Material Conversion
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Solution Overview
Problem
The existing methods for forming self-aligned contacts in semiconductor devices result in undesirable loss of protective gate cap layers and sidewall spacers, leading to increased complexity and difficulty in gate etching processes due to the need for additional thickness to compensate for material consumption during contact etch processes.
Innovation Solution
The method involves forming a layer of insulating material above the source/drain region, performing etching to expose the gate structure, selectively applying an oxidizable material, and undergoing an oxidation process to create an oxide layer before forming conductive contacts, which reduces the consumption of gate cap layers and sidewall spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional self-aligned contact formation is used, then contact alignment is achieved, but gate cap layers and sidewall spacers are consumed during etching
Solution Approach 1:
The patent applies preliminary action by performing the contact etch process before the gate etch process. This sequence allows the contact openings to be formed while the gate cap layers and sidewall spacers are still intact and protective, preventing their consumption during contact etching. The contact openings are self-aligned to the gate structures without requiring the gate protective layers to be thicker than necessary for gate etching alone.
2Reliability
If additional thickness is added to gate cap layers to compensate for material consumption, then protection during contact etching is improved, but gate etching complexity increases
Solution Approach 1:
The patent inverts the conventional sequence of operations. Instead of protecting the gate structures by adding extra thickness to withstand contact etching, the method reverses the order so that contact etching occurs first when the gate structures are not yet present or are protected by sacrificial materials that are removed afterward. This eliminates the need for increased gate cap layer thickness and the associated gate etching complexity.
3Area of stationary object
If feature sizes are reduced to increase device density, then packing density is improved, but short channel effects worsen
Solution Approach 1:
The patent addresses short channel effects by transitioning from planar transistor structures to three-dimensional FinFET structures. This dimensional change allows the channel to extend vertically, increasing the effective channel width without increasing the footprint area. The gate encloses the fin structure on multiple surfaces, providing superior electrostatic control over the channel and reducing short channel effects while maintaining high device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes the loss of protective gate cap layers and sidewall spacers, simplifying the etching processes and maintaining sufficient protection for the gate structures while forming self-aligned contacts efficiently.
Implementation Method 1
performing an oxidation process to convert at least a portion of the oxidizable material to an oxide material
Data Source
AI summary
One method discloses performing an etching process to form a contact opening in a layer of insulating material above at least a portion of a source/drain, region wherein, after the completion of the etching process, a portion of a gate structure of the transistor is exposed, selectively forming an oxidizable material on the exposed gate structure, converting at least a portion of the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to the source/drain region. A novel transistor device disclosed herein includes an oxide material positioned between a conductive contact and a gate structure of the transistor, wherein the oxide material contacts the conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.