Self-Aligned Gate Cutting for Multigate Device Isolation
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Solution Overview
Problem
Existing gate isolation techniques for multigate devices, such as gate-all-around (GAA) devices, face challenges in achieving dense packing of IC features due to non-self-aligned gate cutting methods, which result in increased spacing between active device areas, leading to reduced pattern density and compact cell heights, hindering advancements in advanced IC technology nodes.
Innovation Solution
A self-aligned gate cutting technique is proposed, utilizing an oxide liner to improve inner spacer formation and suspended channel layer uniformity, allowing for smaller spacing between active device areas, and incorporating a dielectric gate isolation fin with high-k and low-k dielectric layers to enhance gate isolation, enabling more compact device packing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-self-aligned gate cutting techniques are used to isolate gates of different GAA devices, then gate isolation is achieved, but spacing between active device areas increases, reducing pattern density
Solution Approach 1:
The patent applies preliminary action by forming the oxide liner on sidewalls of channel regions before gate electrode formation. This pre-positioned liner serves as a reference for subsequent self-aligned gate cutting, enabling precise isolation without requiring additional spacing between devices. The liner is formed in advance to guide the gate cutting process, ensuring accurate alignment and minimizing spacing requirements.
Solution Approach 2:
The oxide liner acts as an intermediary element between the channel region and the gate electrode. It provides a physical reference structure that enables self-aligned gate cutting, serving as a mediator that facilitates precise positioning and isolation of gates while maintaining minimal spacing between adjacent active device areas.
2Area of stationary object
If spacing between active device areas is reduced for dense packing, then pattern density improves, but gate isolation effectiveness deteriorates
Solution Approach 1:
The gate cutting process utilizes the self-aligned mechanism where the oxide liner on the sidewalls automatically guides the etching process to create precise gate isolation. The structure serves itself by using its own formed features (the liner) as the alignment reference, eliminating the need for separate alignment steps and ensuring effective isolation even at minimal spacing between devices.
Solution Approach 2:
The patent replaces traditional mechanical alignment systems with a self-aligned chemical etching process. Instead of using complex mechanical alignment tools and multiple lithography steps, the process uses the oxide liner as a chemical guide for selective etching, substituting mechanical alignment with a chemically-driven self-aligned mechanism that achieves precise isolation at smaller dimensions.
3Ease of manufacture
If conventional gate isolation methods are used, then manufacturing process is simpler, but pattern density and cell height compactness are reduced
Solution Approach 1:
The patent changes the critical parameter of gate alignment from non-self-aligned to self-aligned, fundamentally altering the manufacturing approach. This parameter change enables the use of minimal spacing between devices while maintaining effective isolation, thereby increasing pattern density and reducing cell height without significantly complicating the overall manufacturing process.
Data Source
AI summary
Self-aligned gate cutting techniques are disclosed herein that provide dielectric gate isolation fins for isolating gates of multigate devices from one another. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is greater than the first dielectric constant. The first metal gate and the second metal gate physically contact the first channel layer and the second channel layer, respectively, and the dielectric gate isolation fin.