Self-Aligned Interconnect Cap Structure for Stacked Transistor Alignment
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Solution Overview
Problem
The challenge in fabricating integrated circuit structures between two device levels is exacerbated by misalignment between top and bottom devices and intervening structures on the top device, particularly when devices are densely packed and scaled to smaller dimensions.
Innovation Solution
The solution involves forming an interconnect structure adjacent to a dielectric over a first device structure on a first wafer, depositing a first amorphous semiconducting bonding layer, and bonding the first wafer to a second wafer with a similar bonding layer. This process creates a conductive cap structure through the conversion of the amorphous layer to silicide or germanide, which is self-aligned with the interconnect structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If devices are scaled to smaller dimensions and densely packed, then device density is improved, but misalignment between top and bottom devices worsens
Solution Approach 1:
The interconnect structure is formed in the dielectric layer before wafer bonding, establishing a predefined alignment reference that eliminates alignment issues after bonding occurs
Solution Approach 2:
The interconnect structure serves dual purposes: as an electrical connection element and as a self-aligned reference feature for subsequent wafer bonding, making the structure self-sufficient for alignment
2Quantity of substance
If devices are scaled to smaller dimensions and densely packed, then device density is improved, but fabrication difficulty worsens
Solution Approach 1:
The interconnect structure is formed in the dielectric layer before wafer bonding, establishing a predefined alignment reference that eliminates alignment issues after bonding occurs
Solution Approach 2:
The interconnect structure acts as an intermediary element that facilitates both electrical connection and alignment between stacked devices, simplifying the overall fabrication process
3Ease of operation
If conventional routing methods are used between stacked devices, then connectivity is achieved, but misalignment problems worsen
Solution Approach 1:
The interconnect structure is formed in the dielectric layer before wafer bonding, establishing a predefined alignment reference that eliminates alignment issues after bonding occurs
Solution Approach 2:
The interconnect structure serves dual purposes: as an electrical connection element and as a self-aligned reference feature for subsequent wafer bonding, making the structure self-sufficient for alignment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes via misalignment, overcomes structural impediments in the top transistor, and allows the dielectric separating the device levels to be scaled as needed, thereby enhancing the connectivity and density of integrated circuit structures.
Implementation Method 1
the conversion of the amorphous layer to silicide or germanide
Implementation Method 2
bonding the first wafer to a second wafer with a similar bonding layer
Data Source
AI summary
An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.