Self-Aligned Interconnect Structure for Lower Contact Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in improving integration density and reducing contact resistance in interconnect structures, while also preventing leakage and reliability issues such as time-dependent dielectric breakdown, electromigration, and stress migration.
Innovation Solution
The method involves forming self-aligned structures in an improved interconnect structure, which includes a self-aligned etch-resistant layer and a self-aligned capping material. This is achieved by depositing a plurality of first conductive features in a first dielectric layer, selectively depositing an inhibitor material over the conductive features, an etch-resistant layer over the dielectric layer, and a capping material over the conductive features. An etch stop layer is then deposited, followed by a second dielectric layer and the formation of second conductive features that are electrically coupled to the first conductive features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the contact area between conductive features is increased, then contact resistance is reduced, but the complexity of the interconnect structure increases
Solution Approach 1:
The interconnect structure is segmented into multiple functional layers: a first dielectric layer with conductive features, a second dielectric layer, an etch-resistant layer, and a capping material layer. This segmentation allows each layer to perform its specific function while collectively reducing contact resistance through increased contact area without excessive complexity
Solution Approach 2:
The etch-resistant layer is deposited preliminarily over the first dielectric layer before forming the second dielectric layer. This preliminary action protects the first dielectric layer from damage during subsequent etching processes and provides a controlled interface for increasing contact area between conductive features
Solution Approach 3:
The capping material acts as an intermediary between the conductive features and the second dielectric layer. It is selectively deposited over the conductive features to increase contact area and reduce contact resistance, while the etch-resistant layer serves as an intermediary protective layer during fabrication
2Reliability
If the etch-resistant layer is deposited selectively, then the dielectric layer is protected from damage, but the manufacturing process complexity increases
Solution Approach 1:
The etch-resistant layer is deposited with local quality - it is selectively deposited only in certain regions over the first dielectric layer, not uniformly across the entire substrate. This selective deposition protects specific areas that require protection from subsequent etching while leaving other areas accessible for further processing
Solution Approach 2:
The etch-resistant layer is deposited preliminarily before the second dielectric layer formation and subsequent etching processes. This preliminary protective layer prevents damage to the first dielectric layer during manufacturing while allowing controlled access to conductive features through selective deposition patterns
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the contact area between conductive features, reduces contact resistance, and improves device performance by preventing damage to the dielectric layers and reducing leakage and reliability issues.
Implementation Method 1
An inhibitor material is selectively deposited over the first conductive features, without being deposited on the first dielectric layer
Implementation Method 2
An etch-resistant layer is selectively deposited over the first dielectric layer, without being deposited on the first conductive features or the inhibitor material
Implementation Method 3
A capping material is selectively deposited over the first conductive features, without being deposited on the first dielectric layer or the etch-resistant layer
Data Source
AI summary
An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes providing a first conductive feature in a first dielectric layer; selectively depositing an etch-resistant layer over the first dielectric layer, a sidewall of the etch-resistant layer being coterminous with a sidewall of the first dielectric layer; after selectively depositing the etch-resistant layer, selectively depositing a capping layer over the first conductive feature adjacent the etch-resistant layer, a sidewall of the capping layer being coterminous with a sidewall of the first conductive feature; and forming a second conductive feature over the capping layer, the etch-resistant layer separating the second conductive feature from the first dielectric layer.