Self-Aligned Interconnects with Multi-Metal Gap Fill
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Solution Overview
Problem
Photolithography misalignment in Back End Of the Line (BEOL) metallization leads to patterning defects such as line and vertical interconnect access discontinuities, impacting product reliability and wafer yield.
Innovation Solution
The implementation of a self-aligned interconnect fabrication method that eliminates the need for a hard mask layer, using mandrels and spacers to increase the overlay alignment window, allowing for wider pattern formation and reducing patterning defects through a combination of photolithography and etch processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photolithography alignment methods are used in BEOL metallization, then the fabrication process is simpler, but patterning defects such as line and via discontinuities occur due to misalignment
Solution Approach 1:
The patent applies preliminary action by pre-forming mandrels and spacers that define the alignment window before the actual interconnect patterning step. These structures are created in advance to establish reference points that guide subsequent photolithography alignment, ensuring precise overlay without requiring complex real-time alignment procedures.
Solution Approach 2:
The patent introduces an intermediary alignment window structure composed of mandrels and spacers that mediates between the photolithography system and the interconnect features. This intermediary structure provides physical reference points that facilitate accurate alignment while simplifying the overall fabrication process by decoupling the alignment function from the interconnect formation function.
2Manufacturing precision
If a hard mask layer is used for interconnect patterning, then the patterning process is more controlled, but the fabrication process becomes more complex and alignment issues persist
Solution Approach 1:
The patent extracts the alignment function from the traditional hard mask layer by introducing separate mandrel and spacer structures. These extracted components serve solely as alignment references and are removed after serving their purpose, eliminating the need for a persistent hard mask layer while maintaining patterning precision.
Solution Approach 2:
The patent applies discarding and recovering by using temporary mandrel and spacer structures that are discarded after defining the alignment window. These structures are recovered (removed) after serving their alignment function, allowing the actual interconnect patterning to proceed without the complexity of maintaining a hard mask layer throughout the process.
3Reliability
If the overlay alignment window is increased to reduce patterning defects, then the area required for alignment increases, but this may impact device density
Solution Approach 1:
The patent applies local quality by creating alignment window structures with specific local geometries that maximize alignment functionality within minimal area. The mandrels and spacers are positioned and dimensioned to provide sufficient alignment reference points only where needed, rather than increasing the overall alignment window area, thus maintaining device density while improving reliability.
Data Source
AI summary
The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.