Self-Aligned Interconnects for Memory Arrays
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Solution Overview
Problem
The challenge in forming dense memory arrays is the difficulty in reliably connecting memory cell components, such as bipolar junction transistor (BJT) selectors, to electrodes due to stringent tolerances and limitations in photolithographic manufacturing techniques, which complicates the fabrication process and affects memory density and device performance.
Innovation Solution
The implementation of a self-aligned double patterning (SADP) technique simplifies the formation of electrically conductive interconnects and contacts by reducing the number of lithographic masks required, allowing for more precise alignment and smaller feature dimensions, thereby improving manufacturing yield and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithographic manufacturing techniques are used to connect memory cell components to electrodes, then the fabrication process becomes complicated with stringent tolerances, but memory density and device performance are limited
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into multiple stages through self-aligned double patterning (SADP). First, mandrel structures are formed at relaxed pitch, then spacer structures are deposited and patterned to create final features at half the pitch. This segmentation allows each stage to be optimized independently, achieving high precision without proportionally increasing overall process complexity
Solution Approach 2:
The patent employs preliminary action by forming mandrel structures and spacer structures in advance before final interconnect formation. The mandrels are prepared first as templates, then spacers are deposited conformally on the mandrels. This preliminary structuring enables subsequent self-aligned etching to proceed with high precision while simplifying the final connection formation step
2Reliability
If photolithographic manufacturing techniques with stringent tolerances are used, then connections between memory cell components and electrodes can be formed, but manufacturing yield is reduced
Solution Approach 1:
The patent implements self-service through self-aligned double patterning where the spacer structures automatically align to the mandrel structures without requiring additional lithographic alignment steps. The conformal deposition of spacers on mandrels ensures that the final interconnect positions are determined by the mandrel geometry itself, eliminating alignment errors and improving both connection reliability and manufacturing yield
Solution Approach 2:
By segmenting the patterning into mandrel formation and spacer deposition stages, the patent isolates critical alignment requirements to the spacer-mandrel interface where self-alignment naturally occurs. This segmentation allows relaxed tolerances in mandrel fabrication while maintaining tight final dimensional control, thereby improving manufacturing yield without sacrificing connection reliability
3Ease of manufacture
If conventional lithographic masks are used for forming interconnects, then the fabrication process is simplified, but feature dimensions become larger reducing memory density
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar lithographic patterning to three-dimensional self-aligned double patterning. Mandrels are formed in one dimension with relaxed pitch, then spacers are deposited in the vertical dimension conformally on the mandrels. This adds a vertical dimension to the patterning process, enabling final features at half the original pitch while maintaining fabrication simplicity through self-alignment
Solution Approach 2:
The patent segments the feature formation into mandrel structures and spacer structures, where mandrels provide the template at relaxed pitch and spacers create the final reduced-dimension features. This segmentation allows the fabrication process to remain simple in the mandrel formation step while achieving smaller final feature dimensions through the spacer deposition and removal process
Data Source
AI summary
Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.