Self-Aligned Isolation Fins to Prevent FinFET Gate Collapse
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Solution Overview
Problem
The performance of silicon-based transistors is limited as device dimensions are scaled down, leading to reduced carrier mobility and increased aspect ratios that cause electrical shorts and reduced yield in FinFETs, with dummy gate structures collapsing due to lack of mechanical support.
Innovation Solution
The formation of self-aligned isolation fins by depositing dielectric material in recesses or replacing portions of fins with dielectric material, providing mechanical support and uniform pattern density, which prevents gate collapse and electrical shorts, and reduces parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are scaled down to increase functional density, then production efficiency is improved and costs are lowered, but carrier mobility is reduced and aspect ratios increase causing electrical shorts and gate collapse
Solution Approach 1:
The patent divides the isolation structure into multiple segments: shallow trench isolation regions and self-aligned isolation fins. The self-aligned isolation fins are formed by depositing dielectric material in recesses between active fins, creating a segmented isolation system that provides mechanical support without requiring additional alignment steps, thus preventing gate collapse while maintaining scaled dimensions
Solution Approach 2:
The self-aligned isolation fins act as intermediary structures between the active fins and the shallow trench isolation. These fins provide mechanical support to the gate structure and prevent electrical shorts between adjacent active regions, serving as a mediator that resolves the contradiction between scaled dimensions and reliability
2Manufacturing precision
If dummy gate structures are used to maintain pattern density, then manufacturing uniformity is improved, but mechanical support is insufficient causing gate collapse
Solution Approach 1:
The patent uses composite material structures for the self-aligned isolation fins, combining dielectric material deposited in recesses with the underlying substrate and shallow trench isolation. This composite structure provides both the pattern density uniformity of dummy structures and the mechanical strength needed to prevent gate collapse
3Reliability
If metal source/drain contacts are formed to connect active regions, then electrical connectivity is improved, but parasitic capacitance increases reducing AC gain
Solution Approach 1:
The patent extracts or removes excess metal contact material through planarization processes (chemical mechanical polishing or etch-back) to thin the metal source/drain contacts. This reduces the parasitic capacitance generated by thick metal contacts while maintaining sufficient electrical connectivity between active regions
Data Source
AI summary
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins.