Self-Aligned Hard Mask Patterning for Higher-Density MIM Capacitors

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The limitations in achieving a smaller critical dimension in integrated circuit (IC) technology restrict the number of columns in metal-insulator-metal (MIM) capacitors, thereby reducing the maximum capacitance that can be realized.

Innovation Solution

A method of fabricating IC devices with reduced critical dimensions using a self-aligned mask, involving the deposition and etching of hard mask layers to expose dielectric material with a smaller lateral dimension, allowing for the formation of narrower trenches and columns in MIM capacitors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional photolithographic masks are used, then the critical dimension is limited by mask accuracy and precision, but the number of columns in MIM capacitors is restricted, reducing maximum capacitance

Engineering Contradiction:
Improvecritical dimensionVSAvoidnumber of columns in MIM capacitors
Core Design Contradiction:
Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The mask pattern is segmented into multiple exposure steps, allowing the critical dimension to be defined by etch processes rather than direct photolithography. This enables smaller effective critical dimensions by dividing the patterning process into sequential steps with self-alignment

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from two-dimensional planar patterning to three-dimensional self-aligned structures. By forming mandrels and using conformal deposition, the critical dimension is controlled in the vertical dimension through etch depth rather than horizontal mask features, enabling reduced effective critical dimensions

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If the critical dimension is reduced to increase the number of columns, then capacitance increases, but the mask accuracy and precision requirements become more stringent

Engineering Contradiction:
Improvenumber of columns in MIM capacitorsVSAvoidmask accuracy and precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The process uses self-aligned deposition and etching where previously formed structures serve as their own masks. The conformal deposition on mandrels and the subsequent anisotropic etching automatically align features without requiring additional photolithographic alignment, eliminating mask accuracy limitations

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent replaces the photolithographic mechanical system (masks, aligners, exposure) with a self-aligned chemical-vapor deposition and plasma etching system. This substitution eliminates the fundamental resolution limits of optical photolithography

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Quantity of substance

If more columns are added to MIM capacitors to increase capacitance, then the capacitance increases, but the device footprint must increase without the self-aligned method

Engineering Contradiction:
ImprovecapacitanceVSAvoiddevice footprint
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent utilizes vertical dimension through three-dimensional capacitor structures with extended etch depths. By controlling critical dimension through vertical etch processes rather than horizontal mask features, more columns can be packed into the same planar footprint, increasing capacitance without increasing device area

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250126812A1Integrated circuit fabrication employing self-aligned mask
Publication Date: 2025.04.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250126812A1 patent drawing
  • US20250126812A1 patent drawing
  • US20250126812A1 patent drawing

AI summary

Some embodiments relate to a method that includes depositing a first layer of hard mask material over a layer of dielectric material; etching the first layer of the hard mask material, the etched first layer of hard mask material including an etched portion having a first lateral dimension; depositing a second layer of the hard mask material over the first layer of the hard mask material; etching at least a portion of the second layer of the hard mask material, while allowing a remaining portion of the hard mask material, to expose a portion of the layer of the dielectric material that has a second lateral dimension less than the first lateral dimension; and etching a trench into the layer of the dielectric material at the exposed portion of the layer of the dielectric material.