Self-Aligned MTJ Via Opening for Reliable MRAM Logic Integration
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Solution Overview
Problem
The integration of magnetic random access memory (MRAM) cells with logic circuits in integrated circuits (ICs) faces challenges due to process variations in forming electrical connections, leading to issues such as open or short circuits, which are not compatible with logic processing and result in unreliable connections.
Innovation Solution
A method involving a substrate with distinct regions for memory and logic, where a self-aligned magnetic tunnel junction (MTJ) via opening is formed using an encapsulation stack with specific etch layers, and dielectric spacers are used to create a self-aligned interconnect that is compatible with logic processing, ensuring reliable electrical connections without shorting the MRAM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional planarization and etching processes are used to form interconnects to MRAM cells, then the interconnect can be formed, but process variations cause the interconnect to be either too short (leaving dielectric between interconnect and MRAM cell causing open circuit) or too long (passing through the top layer causing short circuit)
Solution Approach 1:
The patent forms a protrusion structure on the first dielectric layer before forming the interconnect. This preliminary action creates a predetermined height advantage that ensures the interconnect will reach the MRAM cell top layer regardless of etching process variations, preventing both open and short circuit conditions
Solution Approach 2:
The protrusion structure acts as a cushioning feature that compensates for process variations. By pre-forming this structural advantage, the patent creates a buffer zone that absorbs the variability in etching depth, ensuring reliable electrical connection without shorting the MRAM cell
2Reliability
If a middle etch stop layer (ESL) is used to cover process variations, then connection reliability improves, but the RC (resistance-capacitance) increases significantly and it is not compatible with logic processing
Solution Approach 1:
The patent removes the need for an etch stop layer by extracting the height compensation function and integrating it into the dielectric layer structure itself through the protrusion feature. This eliminates the additional ESL layer and its associated complexity while maintaining connection reliability
Solution Approach 2:
The patent merges the height compensation function with the first dielectric layer by forming a protrusion within it. This combines multiple functions (dielectric isolation and height advantage) into a single structural feature, eliminating the need for separate ESL layers and reducing overall process complexity
Data Source
AI summary
In a non-limiting embodiment, a device may be formed having a substrate that has at least a first region and a second region. The first region includes a memory region having at least one magnetic tunnel junction (MTJ) stack, and the second region includes a logic region. An encapsulation stack is formed in the first and second regions and over the MTJ stack(s). The encapsulation stack includes a first layer, a second layer, and a third layer. A single etch may remove at least a portion of the third layer, the second layer, and the first layer of the encapsulation stack to form a self-aligned MTJ via opening over the at least one MTJ stack to form one or more peaks from the encapsulation stack above or around the MTJ stack.