Self-Aligned Phase Change Memory Cell Structure
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Solution Overview
Problem
The challenge in developing high-density memory devices is to align memory cells properly with access devices and word/bit lines while reducing feature sizes and processing costs, especially in phase change memory materials like chalcogenides, where the reset operation requires high current densities and proper alignment is critical.
Innovation Solution
A cross-point programmable memory array is designed using a damascene process where bit and word lines are self-aligned with access devices and memory elements, formed over a semiconductor substrate with specific trench isolation structures, allowing for reduced cell size and lower processing costs without exposing memory materials to etching chemistry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes are reduced to increase memory cell density, then memory cell density is improved, but alignment precision between memory cells and access devices deteriorates
Solution Approach 1:
The patent implements self-aligned fabrication processes where the bit line and word line structures automatically define the positions of access devices and memory elements through sequential formation steps. The first isolation structures (trenches) are formed to define bit line positions, then second isolation structures are formed to define word line positions, with each structure serving as a reference for the next. This self-aligned approach eliminates the need for separate alignment operations, maintaining precision even as feature sizes are reduced to increase memory cell density.
2Ease of manufacture
If the number of masks is reduced to lower processing costs, then manufacturing cost is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent combines multiple functions into shared mask structures. The first isolation structures serve dual purposes as both isolation elements and alignment references for subsequent structures. The second isolation structures similarly serve as both isolation elements and alignment references. This merging of functions reduces the total number of separate mask steps required while maintaining the self-aligned precision needed for high-density memory cells.
3Quantity of substance
If cell size is reduced to increase density, then memory cell density is improved, but reset operation reliability deteriorates due to insufficient current density
Solution Approach 1:
The patent transitions from planar memory cell structures to three-dimensional vertically-aligned structures. The access devices are formed vertically between isolation structures, and memory elements are positioned at the intersections of bit lines and word lines in the vertical dimension. This vertical stacking allows smaller footprint cells while maintaining adequate current density through the phase change material by reducing the lateral contact area between electrodes and the material, thereby enabling reliable reset operations at higher densities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a memory array with reduced cell size and lower processing costs, as it allows for self-aligned word and bit lines with memory elements, maintaining the integrity of the memory material and minimizing the number of required masks.
Implementation Method 1
Phase change based memory materials, such as chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current
Implementation Method 2
The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure
Data Source
AI summary
A programmable memory array is disclosed in which the phase change memory cells are self-aligned at the access devices and at the cross-points of the bit lines and the word lines. A method for making the array employs one line mask to define the bit lines and another line mask to define the word lines. The front end of line (FEOL) memory cell elements are in the same layer as the polysilicon gates. The bit lines and the word lines intersect over the devices, and the memory cell elements are formed at the intersections of the bit lines and the word line.