Self-Aligned Source and Drain Contacts in Double Gate FET
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Solution Overview
Problem
The existing dual gate MOSFET fabrication methods face challenges such as current path deterioration due to imperfect interfaces, varying crystallographic orientations affecting current drivability, complex source/drain junction formation, and impractical fin dimensions, leading to limitations in circuit design and performance.
Innovation Solution
A method involving the formation of a transistor structure on a silicon-on-insulator substrate with a gate region separated by a dielectric layer, using ion implantation to create high impurity regions below source and drain areas and a heavily-damaged region below the gate, allowing for self-aligned source and drain regions and a channel region with precise impurity profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-angle implantations are used to reach the whole volume of fin parts, then source/drain junction formation is achieved, but the process becomes complicated and requires sufficient distance between fins
Solution Approach 1:
The method performs preliminary actions by forming sacrificial oxide layers and selectively removing material before final source/drain junction formation. The sacrificial oxide is grown and patterned in advance to define the exact implantation regions, allowing subsequent low-angle implantations to achieve precise junction formation without requiring complex high-angle procedures or large spacing between fins.
2Manufacturing precision
If multiple fins are used to achieve practical aspect ratios, then fin width can be increased, but all fins must be exactly the same and cannot be spaced densely
Solution Approach 1:
The invention segments the fin structure into multiple identical fins that can be independently formed using the same fabrication process. Each fin is created through identical sacrificial oxide patterning and material deposition steps, ensuring uniform dimensions across all fins. This segmentation approach allows standardization while maintaining manufacturing precision.
Solution Approach 2:
The method enables parameter changes by allowing flexible adjustment of fin spacing and dimensions through the sacrificial oxide layer thickness and patterning parameters. The sacrificial oxide can be grown to different thicknesses and patterned with different geometries, providing circuit designers with flexibility in optimizing device performance without compromising manufacturing precision.
3Power
If fin height is increased to achieve higher current drive, then current drive capability improves, but fin width must be reduced to maintain aspect ratio constraints
Solution Approach 1:
The invention transitions from controlling device characteristics primarily through fin width to utilizing fin height as the primary dimensional parameter for current drive control. By forming fins with standardized widths through sacrificial oxide patterning and allowing variable heights through controlled epitaxial growth or deposition, the method enables current drive optimization in the vertical dimension while maintaining manufacturing precision in the lateral dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of FET devices with improved current drive and reduced parasitic capacitance, allowing for existing circuit designs to be retained without the need for significant redesign, and can be applied to both MOSFET and bipolar devices.
Implementation Method 1
the formation of high level impurity or heavily-damaged regions by ion implantation, exposing the open area to an ion beam with the demarcating layer region and the gate region acting as implantation mask
Data Source
AI summary
A method of forming a transistor structure on a substrate (SOI) is disclosed, wherein the substrate comprises a supporting Si layer, a buried insulating layer, and a top Si layer. The method comprises forming a gate region of the transistor structure on the top Si layer, wherein the gate region is separated from the top Si layer by a dielectric layer, and wherein the top Si layer comprises a high dopant level. The method further comprises forming an open area on the top Si layer demarcated by a demarcating oxide and/or resist layer region, forming high level impurity or heavily-damaged regions by ion implantation, and exposing the open area to an ion beam, wherein the ion beam comprises a combination of beam energy and dose, and wherein the demarcating layer region and the gate region act as an implantation mask.