Self-Aligned Source Gate Tunnel Junction FET
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Solution Overview
Problem
Conventional nitride-based tunnel junction field effect transistors face challenges in precision alignment of gate and source electrodes, affecting the control over the tunnel junction's conductive state and threshold voltage due to separate photolithography layers used in fabrication.
Innovation Solution
The method involves self-alignment of the gate electrode to the source electrode and the channel layer, using the gate electrode as an etch mask to form a trench in the epitaxial structure, allowing the source metal to form a Schottky junction with the channel layer, thereby improving control over the electrical field and conductive state modulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate photolithography layers are used for gate and source electrodes, then fabrication flexibility is maintained, but alignment precision between gate and source electrodes deteriorates
Solution Approach 1:
The patent combines the gate electrode formation and source electrode alignment into a single photolithography step. The gate electrode pattern serves as the alignment reference for the source electrode, eliminating the need for separate photolithography layers and their associated alignment errors. This merging of steps directly improves alignment precision while reducing process complexity.
Solution Approach 2:
The gate electrode pattern automatically serves as the alignment mask for the source electrode formation. By using the gate electrode itself as the reference structure, the system achieves self-alignment without requiring additional external alignment marks or complex multi-layer photolithography processes.
2Manufacturing precision
If self-alignment method is used, then alignment precision is improved, but the need for separate photolithography layers is reduced
Solution Approach 1:
The patent merges the gate and source electrode formation into a single photolithography step, where the gate electrode pattern directly defines the alignment for the source electrode. This reduces the number of fabrication steps while improving alignment precision, making the overall process easier to manufacture.
Solution Approach 2:
The gate electrode pattern serves as its own alignment reference for the source electrode formation. This self-service approach eliminates the need for separate alignment marks or additional photolithography layers, simplifying the fabrication process while maintaining high alignment precision.
3Ease of manufacture
If conventional alignment methods are used, then fabrication process is simpler, but control over tunnel junction conductive state deteriorates
Solution Approach 1:
The gate electrode pattern automatically defines the precise alignment for the source electrode, ensuring optimal positioning for tunnel junction formation. This self-service alignment method maintains fabrication simplicity while significantly improving the control over the tunnel junction's conductive state through precise spatial positioning.
Solution Approach 2:
The invention changes the alignment parameter from conventional separate-layer photolithography to a single-layer self-aligned approach. This parameter change in the fabrication process enables precise control over the tunnel junction geometry and conductive state while maintaining ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the precision and control over the tunnel junction's operation, reducing the need for precise stepper alignment and improving the modulation of the conductive state, leading to improved device performance.
Implementation Method 1
A reactive ion etching (RIE) mesa isolation using a chlorine/helium (Cl2/He) inductively coupled plasma etch process may be used to define a device mesa.
Implementation Method 2
An ohmic drain electrode 18 is deposited using electron-beam (e-beam) evaporation and a rapid thermal anneal.
Data Source
AI summary
Methods of forming a transistor include providing a semiconductor epitaxial structure including a channel layer and barrier layer on the channel layer, forming a gate electrode on the barrier layer, etching the semiconductor epitaxial structure using the gate electrode as an etch mask to form a trench in the semiconductor epitaxial structure, and depositing a source metal in the trench. The trench extends at least to the channel layer, and the source metal forms a Schottky junction with the channel layer. Related semiconductor device structures are also disclosed.