Self-Aligned Via Hardmask Stack for Sub-22 Nm Metal Pitch
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Solution Overview
Problem
Conventional self-alignment techniques for vias in semiconductor manufacturing face challenges with edge placement errors exceeding ¼ of the metal pitch, leading to unintended via formations and short circuits, limiting the minimum pitch to 22 nm, which hinders further area scaling in semiconductor devices.
Innovation Solution
A top-down self-alignment method using a hardmask layer stack with etch-selective materials and sidewall spacers to form composite etch masks, allowing via and trench patterns to self-align, extending the edge placement error tolerance to ¾ of the metal pitch, enabling patterning at sub-22 nm pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional self-alignment techniques are used for via formation, then via alignment is achieved, but edge placement errors exceed ¼ of metal pitch causing unintended via formations and short circuits
Solution Approach 1:
The patent divides the single patterning step into multiple sequential patterning steps (first pattern, second pattern, third pattern) with intermediate etching and spacer formation steps. This segmentation allows each step to be controlled within tighter tolerances, achieving cumulative alignment precision that exceeds what a single step could provide, thereby preventing short circuits while maintaining via alignment.
Solution Approach 2:
The patent performs preliminary patterning actions to create mandrels and spacers that define subsequent etch regions. By pre-establishing these alignment reference structures before final via formation, the process ensures that vias are positioned correctly relative to metal lines, preventing both misalignment and unintended short circuits.
2Area of stationary object
If minimum pitch is reduced below 22 nm for area scaling, then device area is reduced, but edge placement errors cause manufacturing variability to increase
Solution Approach 1:
The patent transitions from two-dimensional planar patterning to three-dimensional spacer-based patterning. By forming vertical spacer structures on mandrels and using them as etch masks, the process adds a dimensional element that enables sub-22 nm pitch patterning with controlled accuracy, overcoming the limitations of conventional 2D lithographic resolution.
Solution Approach 2:
The spacer structures self-align to the mandrels through conformal deposition, automatically establishing precise spatial relationships without requiring additional alignment steps. This self-service mechanism ensures consistent pitch control at sub-22 nm dimensions, reducing manufacturing variability while enabling area scaling.
3Manufacturing precision
If multiple hardmask layers with etch-selective materials are used, then self-alignment tolerance is extended to ¾ of metal pitch, but process complexity increases
Solution Approach 1:
The patent assigns different etch-selective materials to different hardmask layers (first hardmask, second hardmask, third hardmask) based on their specific functional requirements in each patterning step. Each layer's material composition is optimized for its local role in the sequence, enabling precise control of etch processes while managing overall process complexity through targeted material selection.
Solution Approach 2:
The patent employs a composite hardmask layer stack with multiple materials that have complementary etch selectivities. This composite structure allows sequential etching of different layers with appropriate selectivity ratios, achieving extended self-alignment tolerance of ¾ metal pitch while organizing process complexity into manageable sequential steps.
Data Source
AI summary
A process includes forming, over a dielectric layer, a hardmask stack including a first layer below a second layer below a third layer below a fourth layer. The first and third layers include a different hardmask material from the second and fourth layers. A trench pattern including sidewall spacer structures is formed over the hardmask stack. The fourth layer is etched in a first region. The fourth and third layers are etched in a second region. The fourth and third layers are etched in a third region. The fourth layer is etched in a fourth region. The second and first layers are etched in the second and third regions. The third layer is etched in the first and fourth regions. In the dielectric layer, trenches are formed in the first and fourth regions, and via openings, deeper than the trenches, are formed in the second and third regions.