Self-Aligned Via Integration with Sacrificial Blocks

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Solution Overview

Problem

Conventional fully aligned via schemes in semiconductor devices result in yield and reliability issues due to larger than ideal overlay errors and increased resistance-capacitance product in shrinking dimensions, particularly in BEOL processing.

Innovation Solution

The method involves forming self-aligned vias using top level line double patterns, where sacrificial blocks are used to create vias that align with both top and bottom conductive lines, eliminating the need for via level litho and reducing line-to-via alignment errors, contact resistance, and improving via reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional fully aligned via schemes are used, then via alignment is achieved, but overlay errors increase and reliability deteriorates

Engineering Contradiction:
Improvevia alignmentVSAvoidchip yield and reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The via formation process uses self-aligned vias (SAV) where the via placement is automatically aligned to the conductive lines through the patterning process itself, eliminating the need for separate via level lithography and reducing overlay errors. The sacrificial blocks are formed perpendicular to the first conductive lines, and vias are formed directly underneath them, ensuring automatic alignment without additional alignment steps.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

Sacrificial blocks are formed in advance perpendicular to the first conductive lines before via formation. These sacrificial blocks serve as placeholders that define the exact via locations. The vias are then formed directly underneath the sacrificial blocks, ensuring precise alignment before the sacrificial blocks are removed and the vias are filled with conductive material.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If dielectric space between copper lines and vias is reduced, then integration density improves, but yield and reliability issues increase

Engineering Contradiction:
Improveintegration densityVSAvoidyield and reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The self-aligned via process ensures that vias are automatically positioned with optimal spacing from conductive lines through the sacrificial block methodology. This maintains adequate dielectric space while achieving high integration density, as the via placement is precisely controlled by the sacrificial block positions rather than relying on overlay accuracy.

Inventive Principle:
Principle #25Self-service

3Manufacturing precision

If top level line double patterns are used, then alignment precision improves, but process complexity increases

Engineering Contradiction:
Improvealignment precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The via formation process is segmented into distinct stages: forming sacrificial blocks perpendicular to first conductive lines, forming vias underneath the sacrificial blocks, removing the sacrificial blocks, and filling the vias with conductive material. This segmentation allows each step to be optimized independently while maintaining overall alignment precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Sacrificial blocks serve as intermediary structures that facilitate precise via alignment. These temporary structures are formed perpendicular to the first conductive lines, define the via locations, and are subsequently removed after serving their alignment purpose. The intermediary sacrificial blocks enable precise alignment without requiring complex direct patterning of the vias themselves.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11244860B2Double patterning interconnect integration scheme with SAV
Publication Date: 2022.02.08 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11244860B2 patent drawing
  • US11244860B2 patent drawing
  • US11244860B2 patent drawing

AI summary

A method is presented for forming self-aligned vias by employing top level line double patterns. The method includes forming a plurality of first conductive lines within a first dielectric material, recessing one or more of the plurality of first conductive lines to define first openings, filling the first openings with a second dielectric material, and forming sacrificial blocks perpendicular to the plurality of first conductive lines. The method further includes forming vias directly underneath the sacrificial blocks, removing the sacrificial blocks, and constructing a plurality of second conductive lines such that the vias align to both the plurality of first conductive lines and the plurality of second conductive lines.