Self-Aligning Chiplet Stacking in Semiconductor Packages
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Solution Overview
Problem
Traditional two-dimensional integrated circuits face physical limits in density and complexity due to the need for more complex designs when increasing components per chip, and three-dimensional integrated circuits face challenges with carrier substrate size, joint height, and flux residue in traditional chip stacking processes.
Innovation Solution
The development of a self-aligning chiplet and stacking method using recesses in a substrate with similarly angled sidewalls, allowing for improved alignment and bonding of chiplets within these recesses, enabling increased misalignment tolerance and reduced final misalignment, and facilitating the integration of heterogeneous chiplets on a single wafer without the need for an interposer or through-substrate vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional chip stacking with solder joints is used, then electrical connections are formed between chips, but misalignment and flux residue issues occur
Solution Approach 1:
The patent introduces an intermediary structure (recess with bonding pad) between the chip and substrate that facilitates precise alignment and bonding. The recess acts as a mechanical guide that receives the chip's protrusion, ensuring accurate positioning while the bonding pad provides a dedicated bonding interface, thereby resolving both alignment precision and connection reliability requirements.
Solution Approach 2:
The patent replaces the traditional solder-based mechanical bonding system with a recess-protrusion mechanical interlock system. This substitution eliminates the need for solder joints and flux, thereby eliminating flux residue issues while maintaining electrical connection reliability through direct contact between bonding pads.
2Reliability
If carrier substrate is used for wire bonding, then electrical connections are established, but the substrate size must be larger than the chips
Solution Approach 1:
The patent transitions from a planar wire bonding approach to a vertical stacking approach. By forming electrical connections in the vertical dimension through recess-protrusion interlocking and direct pad-to-pad bonding, the substrate can be reduced to the minimum area required for the chip itself, eliminating the need for a larger carrier substrate.
3Quantity of substance
If more devices are integrated into one chip, then circuit density increases, but design complexity increases
Solution Approach 1:
The patent divides the integrated circuit into multiple separate chips, each containing a subset of devices. These segmented chips are then stacked vertically and interconnected through the recess-protrusion bonding system, achieving high component density while keeping individual chip designs simpler and more manageable.
4Reliability
If traditional chip stacking is used, then chips are bonded together, but joint height and flux residue create limitations
Solution Approach 1:
The patent extracts and eliminates the solder joint and flux components from the chip bonding process. By using a recess-protrusion mechanical interlock system with direct pad bonding, the complex multi-step soldering process is replaced with a simpler, more reliable mechanical and electrical bonding approach that eliminates joint height variations and flux residue problems.
Data Source
AI summary
Semiconductor packages and methods of forming the same are disclosed. Embodiments include forming a first recess in a first substrate, wherein a first area of an opening of the first recess is larger than a second area of a bottom of the first recess. The embodiments also include forming a first device, wherein a third area of a top end of the first device is larger than a fourth area of a bottom end of the first device. The embodiments also include placing the first device into the first recess, wherein the bottom end of the first device faces the bottom of the first recess, and bonding a sidewall of the first device to a sidewall of the first recess.