Self-Reset DUT Testing With Simulated PCIe Stable-Power Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional test systems face inefficiencies in initializing and resetting devices under test (DUTs) due to the absence of an externally generated PERST signal, leading to interruptions and energy waste, especially when the test system CPU/host does not power down during testing.
Innovation Solution
A test system with a functional ASIC component generates a simulated reset stable indication, allowing devices like FPGAs to initialize without an external reset signal, using a PCIe compatible bus to simulate stable power conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the test system CPU/host is turned off and on to initialize or reset a test system component, then the component can be reset, but all or most testing operations are interrupted and cancelled, resulting in waste of time and energy
Solution Approach 1:
A PERST signal generator component is introduced as an intermediary between the host and the test system component. This generator produces the PERST reset signal independently without requiring the host to power down, thereby enabling component reset while maintaining continuous testing operations. The intermediary decouples the reset function from the host power cycle, eliminating the need to interrupt testing.
Solution Approach 2:
The PERST signal generator is pre-configured to generate reset signals on demand before actual reset operations are needed. The generator can be programmed with reset timing and duration parameters in advance, allowing immediate execution of reset operations without system interruption. This preliminary preparation enables rapid reset execution while testing continues uninterrupted.
2Productivity
If the test system CPU/host does not power down during testing, then testing operations can continue without interruption, but no PERST signal is provided to downstream components for reset initialization
Solution Approach 1:
The PERST signal generator serves as a mediator that bridges the gap between the continuously running host and the components requiring reset signals. It independently generates PERST signals according to programmed parameters, eliminating the need for host power cycling while ensuring reset functionality remains available. This intermediary solution maintains both productivity and operational ease.
Solution Approach 2:
The PERST signal generator is configured to autonomously generate reset signals based on pre-programmed parameters without requiring host intervention or power cycling. The generator self-manages the reset signal generation, timing, and duration, enabling components to receive proper reset initialization while the host continues testing operations uninterrupted. This self-service capability resolves the contradiction between continuous operation and reset availability.
Data Source
AI summary
Efficient and effective testing systems and methods are presented. In one embodiment, a test system includes: a system comprising a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the test board includes a functional/interface application specific integrated circuit (ASIC) component, and the test board includes a component configured to generate a simulated indication that a resource from a source external to the functional/interface ASIC is stable, and a tester configured to direct testing of the plurality of DUTs, wherein the tester is communicatively coupled to the functional/interface ASIC. In one embodiment the ASIC is a field programmable gate array (FPGA).