Programmable Self-Test Controller for Electronic Devices
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Solution Overview
Problem
Current self-test solutions for electronic devices, such as those in the automotive sector, lack flexibility and portability, are prone to latency issues, and are not well-suited for real-time monitoring, making them inefficient for detecting faults and ensuring safety in power control applications.
Innovation Solution
A programmable self-test system with a configurable digital controller that manages control signals, performs real-time tests, and communicates with a host controller, utilizing a finite state machine for concurrent self-test execution and flexible configuration via a serial peripheral interface, enabling standardization and reduced development costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional self-test solutions (Mentor Tessent based on DFT proprietary architecture) are used, then self-test capability is provided for specific applications, but flexibility and portability between products/platforms deteriorate
Solution Approach 1:
The patent implements a universal self-test architecture that can be ported across multiple products and platforms. The test sequencer and control logic are designed as reusable IP cores that can be integrated into different electronic devices, providing the same self-test functionality across diverse applications without requiring application-specific custom design.
Solution Approach 2:
The system employs a programmable and configurable test sequencer that can dynamically adapt to different test scenarios and device states. The finite state machine (FSM) allows the self-test system to transition between different operational modes and configurations, enabling flexible control over test execution based on real-time conditions.
2Reliability
If serial access approach is used, then self-test capability is provided, but execution speed deteriorates due to intrinsic slowness
Solution Approach 1:
The patent segments the self-test execution into parallel independent test channels or modules. Instead of sequentially accessing test resources through a single serial interface, multiple test operations can be initiated and executed simultaneously through separate control paths, thereby increasing overall execution speed while maintaining comprehensive test coverage.
3Reliability
If ad-hoc solutions specific to certain devices are used, then device-specific test requirements are met, but compatibility with programmable control by host controller deteriorates
Solution Approach 1:
The self-test system is designed with a standardized interface and control mechanism that can be uniformly programmed by a host controller across different device types. The test sequencer accepts generic control commands and configurations, allowing centralized management and programmable control while still accommodating device-specific test requirements through configurable parameters rather than custom architecture.
4Reliability
If conventional self-test architecture is used, then self-test functionality is provided, but development costs and development cycles increase
Solution Approach 1:
The patent provides pre-designed and pre-validated self-test IP cores and architectural frameworks that can be directly integrated into new product designs. This preliminary preparation of test architecture eliminates the need for lengthy custom design, simulation, and verification cycles, thereby reducing development time and costs while ensuring robust self-test functionality.
Data Source
AI summary
An electronic device such as an e-fuse includes analog circuitry configured to be set to one or more self-test configurations. To that effect the device has self-test controller circuitry in turn including: an analog configuration and sensing circuit configured to set the analog circuitry to one or more self-test configurations and to sense test signals occurring in the analog circuitry set to such self-test configurations, a data acquisition circuit configured to acquire and convert to digital the test signals sensed at the analog sensing circuit, and a fault event detection circuit configured to check the test signals converted to digital against reference parameters. The device includes integrated therein a self-test controller configured to control parts or stages of the device to configure circuits, acquire data and control test execution under the coordination of a test sequencer.