Semi-Digital DLL Phase Alignment for Low-Jitter Pixel Clocks
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Solution Overview
Problem
Conventional DLL circuits fail to meet the requirements of higher resolution displays that necessitate higher frequency pixel clocks and smaller DLL jitter, as they are unable to achieve sufficient locking precision.
Innovation Solution
A semi-digital DLL circuit with a multi-phase phase locked loop, phase detector, phase selector, and delay circuit that generates and adjusts phase signals to align a reference signal with a feedback signal, incorporating a method to detect both integral and fractional phase errors and shift the phase accordingly to minimize jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DLL circuits are used, then the circuit structure is simple, but the locking precision is insufficient for high-resolution displays
Solution Approach 1:
The phase detector is segmented into two independent detectors: a first phase detector for detecting integer phase errors and a second phase detector for detecting fractional phase errors. This segmentation allows each detector to be optimized for its specific detection task, improving overall locking precision while maintaining manageable circuit complexity through functional division.
Solution Approach 2:
The invention introduces a fractional phase error detection dimension in addition to the traditional integer phase error detection. By adding the second phase detector that operates in the fractional domain, the system achieves higher precision phase measurement without simply increasing the complexity of the original detection mechanism.
2Productivity
If higher frequency pixel clocks are used for higher resolution displays, then the display resolution improves, but the DLL jitter increases
Solution Approach 1:
The invention implements a dual-feedback mechanism where both integer and fractional phase errors are detected and fed back to the delay line controller. This comprehensive feedback approach allows the system to continuously correct phase deviations at both integer and fractional levels, suppressing jitter even at higher operating frequencies required for high-resolution displays.
Solution Approach 2:
The system dynamically adjusts the delay line parameters based on both integer and fractional phase error measurements. By changing the delay parameters in response to precise phase error detection, the system maintains stable operation and low jitter across a wide range of pixel clock frequencies, enabling high-resolution display performance.
Data Source
AI summary
A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal.